Configurable IC with routing circuits with offset connections

• US 7,576,564 B2
• Filed: 10/08/2007
• Issued: 08/18/2009
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Teig, Steven, Huang, Randy Renfu, Hutchings, Brad
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US11/868,959
• Publication Number:
  US 20080100339A1
• Time in Patent Office: 680 Days
• Field of Search: 326 38- 41, 326/47
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Claims

1. An integrated circuit (“

IC”

) comprising;

a plurality of configurable tiles arranged in a tile arrangement,

each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits;

wherein at least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement; and

wherein said at least one direct connection has an intervening buffer circuit that is not an interconnect circuit.

2. The IC of claim 1, wherein a plurality of routing circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

3. The IC of claim 1, wherein the second circuit is another routing circuit.

4. The IC of claim 3, wherein the second circuit receives output of the first circuit through the direct connection.

5. The IC of claim 1, wherein the second circuit is a logic circuit.

6. The IC of claim 1, wherein the second circuit receives output of the first circuit through the direct connection.

7. The IC of claim 1 further comprising a plurality of configurable input-select circuits for receiving and selecting inputs for configurable logic circuits, wherein the second circuit is a configurable input-select circuit that through the direct connection receives output of the first routing circuit.

8. The IC of claim 1, wherein each of a plurality of routing circuits of each particular tile in a set of tiles has at least one direct connection with at least one other circuit of another tile that does not neighbor the particular tile and that is not aligned horizontally or vertically with the particular tile in the tile arrangement.

9. The IC of claim 1, wherein the direct connection does not include any intervening circuits.

10. The IC of claim 9, wherein the direct connection includes a set of wire segments and a set of vias.

11. The IC of claim 1, wherein the direct connection further includes a set of wire segments.

12. The IC of claim 1, wherein the plurality of tiles includes at least 300 tiles.

13. The IC of claim 1, wherein the plurality of tiles includes at least 1000 tiles.

14. The IC of claim 1, wherein two tiles do not neighbor each other in the tile arrangement when the two tiles are not adjacent to each other in any direction, including horizontal, vertical, and diagonal directions.

17. The IC of claim 1, wherein said intervening buffer circuit is a first intervening buffer circuit, said direct connection comprises a second intervening buffer circuit.

18. The IC of claim 1, wherein said intervening buffer circuit is an inverter.

15. An integrated circuit (“

IC”

) comprising;

a plurality of configurable tiles arranged in a tile arrangement, wherein the tile arrangement comprises rows and columns of tiles,

each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals to configurable logic circuits and to other configurable routing circuits;

wherein at least a first routing circuit of a first tile has at least one direct connection with a second routing circuit of a second tile that is not aligned horizontally or vertically with and is at least three rows or three columns of tiles away from the first tile in the tile arrangement, and through the direct connection, the first routing circuit provides an input signal to the second routing circuit.

16. The IC of claim 15, wherein the first routing circuit has a fan out greater than one.

19. A device comprising:

an integrated circuit (“

IC”

) comprising;

a plurality of configurable tiles arranged in a tile arrangement,

each configurable tile having a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits;

wherein at least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement; and

wherein said at least one direct connection has an intervening buffer circuit that is not an interconnect circuit.