Low-voltage differential signal driver for high-speed digital transmission

• US 7,576,567 B2
• Filed: 05/31/2006
• Issued: 08/18/2009
• Est. Priority Date: 05/31/2006
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Jiang, Jian Hong
• Primary Examiner(s): Tan; Vibol
• Assistant Examiner(s): Tabler; Matthew C
• Application Number:
  US11/421,239
• Publication Number:
  US 20070279094A1
• Time in Patent Office: 1,175 Days
• Field of Search: None
• US Class Current: 326/83
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 19/094 using field-effect transistors

Abstract

A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases a differential output voltage.

Claims

1. A low-voltage differential signal driver for high-speed digital transmission, comprising:

a first current source operable to receive a signal in a first type and convert the signal into a second type, wherein the first current source comprises a set of at least two transistors and a switch associated with each transistor, the switch operable to control current flow into a gate of a transistor;

a common-mode feedback circuit coupled to the first current source and operable to control the first current source by controlling a common-mode voltage; and

a cascode current mirror coupled to the first current source, the cascode current mirror provides an impedance level that increases a differential output voltage and increases a voltage headroom available to output the signal, wherein the cascode current mirror comprises;

a second current source operable to receive the signal in the second type and convert the signal into the first type, wherein the second current source comprises a first set of at least two transistors coupled in parallel with a second set of at least two transistors and a switch associated with each transistor, the switch operable to control current flow into a gate of a transistor; and

a reference current source operable to bias a current, wherein the reference current source comprises;

a first transistor; and

a second transistor coupled in series with a third transistor, wherein the first and second transistors have a common terminal that goes to the first set of at least two transistors and the third transistor has a terminal that goes to the second set of at least two transistors.

2. The driver of claim 1, wherein the signal in the first type is a digital signal, the signal in the second type is an analog signal, and the second current source is an analog-to-digital converter structured current source.

3. The driver of claim 1, wherein the signal in the first type is a digital signal, the signal in the second type is an analog signal, and the first current source is a digital-to-analog converter structured current source.

4. The driver of claim 1, wherein the cascode current mirror comprises a plurality of n-channel metal-oxide semiconductor field effect transistors.

5. The driver of claim 1, wherein the first current source comprises a plurality of p-channel metal-oxide semiconductor field effect transistors.

7. The driver of claim 1, wherein the first converter and the cascode current mirror are operable to drive signals at an Ethernet switch.

6. A low-voltage differential signal driver for high-speed digital transmission, comprising:

a first current source operable to receive a signal in a first type and convert the signal into a second type, wherein the first current source comprises a set of at least two transistors and a switch associated with each transistor, the switch operable to control current flow into a gate of a transistor; and

a common-mode feedback circuit coupled to the first current source and operable to control the first current source by controlling a common-mode voltage; and

a cascode current mirror coupled to the first current source, the cascode current mirror provides an impedance level that increases a differential output voltage to greater than 400 mV and increases a voltage headroom available to output the signal, wherein the cascode current mirror comprises;

a second current source operable to receive the signal in the second type and convert the signal into the first type, wherein the second current source comprises a first set of at least two transistors coupled in parallel with a second set of at least two transistors and a switch associated with each transistor, the switch operable to control current flow into a gate of a transistor; and

a reference current source operable to bias a current, wherein the reference current source comprises;

a first transistor; and

a second transistor coupled in series with a third transistor, wherein the first and second transistors have a common terminal that goes to the first set of at least two transistors and the third transistor has a terminal that goes to the second set of at least two transistors.

8. A method for driving a low-voltage differential signal for high-speed digital transmission, comprising:

receiving a signal in a first type at a first current source;

converting the signal into a second type at the first current source, wherein the first current source comprises a set of at least two transistors and a switch associated with each transistor, the switch operable to control current flow into a gate of a transistor;

controlling the first current source by controlling a common-mode voltage;

providing a signal path through a low-voltage differential signal driver, wherein the signal continues through a cascode current mirror, the cascode current mirror providing an impedance level that increases a differential output voltage and increases a voltage headroom available to output the signal;

receiving the signal in the second type at a second current source;

converting the signal into the first type at the second current source, wherein the second current source comprises a first set of at least two transistors coupled in parallel with a second set of at least two transistors and a switch associated with each transistor, the switch operable to control current flow into a gate of a transistor; and

biasing a current at a reference current source, wherein the reference current source comprises;

a first transistor; and

a second transistor coupled in series with a third transistor, wherein the first and second transistors have a common terminal that goes to the first set of at least two transistors and the third transistor has a terminal that goes to the second set of at least two transistors.

9. The method of claim 8, further comprising:

receiving a signal in the second type; and

converting the signal to the first type.

10. The method of claim 8, wherein the signal in the first type is a digital signal, and the signal in the second type is an analog signal.

11. The method of claim 8, wherein the differential output voltage is greater than 400 mV.

12. The method of claim 8, wherein providing a signal path comprises driving the signal at an Ethernet switch.

13. A system for driving a low-voltage differential signal for high-speed digital transmission, comprising:

means for receiving a signal in a first type at a first current source;

means for converting the signal into a second type at the first current source, wherein the first current source comprises a set of at least two transistors and a switch associated with each transistor, the switch operable to control current flow into a gate of a transistor;

means for controlling the first current source by controlling a common-mode voltage;

means for providing a signal path through a low-voltage differential signal driver, wherein the signal continues through a cascode current mirror, the cascode current mirror providing an impedance level that increases a differential output voltage and increases a voltage headroom available to output the signal;

means for receiving the signal in the second type at a second current source;

means for converting the signal into the first type at the second current source, wherein the second current source comprises a first set of at least two transistors coupled in parallel with a second set of at least two transistors and a switch associated with each transistor, the switch operable to control current flow into a gate of a transistor; and

means for biasing a current at a reference current source, wherein the reference current source comprises;

a first transistor; and

a second transistor coupled in series with a third transistor, wherein the first and second transistors have a common terminal that goes to the first set of at least two transistors and the third transistor has a terminal that goes to the second set of at least two transistors.

14. The system of claim 13, further comprising:

means for receiving a signal in the second type; and

means for converting the signal to the first type.

15. The system of claim 13, wherein the signal in the first type is a digital signal, and the signal in the second type is an analog signal.

16. The system of claim 13, wherein the differential output voltage is greater than 400 mV.

17. The system of claim 13, further comprising means for driving the signal at an Ethernet switch.