Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC)
First Claim
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1. An analog to digital converter (ADC) comprising:
- a first sample and hold amplifier (SHA) receiving an input signal and providing an amplified version of the input signal on a first path;
a second SHA receiving the input signal and also providing an amplified version of the input signal on a second path;
a stage of an ADC generating a sub-code from the input signal, the stage including;
a flash ADC sampling the input signal on the first path from the first SHA, and generating a sub-code representing a strength of the input signal; and
a DAC-Subtractor circuit sampling the input signal on the second path from the second SHA, the first circuit generating an amplified residue signal for processing by a next stage that forms at least a portion of the ADC.
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Abstract
A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
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Citations
9 Claims
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1. An analog to digital converter (ADC) comprising:
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a first sample and hold amplifier (SHA) receiving an input signal and providing an amplified version of the input signal on a first path; a second SHA receiving the input signal and also providing an amplified version of the input signal on a second path; a stage of an ADC generating a sub-code from the input signal, the stage including; a flash ADC sampling the input signal on the first path from the first SHA, and generating a sub-code representing a strength of the input signal; and a DAC-Subtractor circuit sampling the input signal on the second path from the second SHA, the first circuit generating an amplified residue signal for processing by a next stage that forms at least a portion of the ADC. - View Dependent Claims (2, 3)
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4. A device comprising:
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a processor processing a plurality of digital values; and an ADC to generate said plurality of digital values, the ADC including; a first SHA receiving the input signal and providing an amplified version of input signal on a first path; a second SHA receiving the input signal and also providing an amplified version of the input signal on a second path; a flash ADC sampling the input signal on the first path from the first SHA, and generating a sub-code representing a strength of the input signal; and a the DAC-Subtractor circuit sampling the input signal on the second path from the second SHA, the quantizer and the first circuit being at least a portion of a stage of the ADC, the first circuit generating an amplified residue signal for processing by a next stage that forms at least a portion of the ADC. - View Dependent Claims (5, 6, 7, 8)
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9. A method of generating a sub-code from an input signal using a stage of an ADC, said method comprising:
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amplifying the input signal using a first amplifier and a second amplifier, wherein the first and second amplifiers are separate amplifiers; providing an output of the first amplifier on a first path to a flash ADC; providing an output of the second amplifier on a second path to a DAC-Subtractor circuit; generating a sub-code by the flash ADC based at least in part on a signal received on the first path from the first amplifier; and generating an amplified residue signal for processing by a next stage based on a signal received by the DAC-Subtractor circuit on the second path from the second amplifier, wherein the next stage forms at least a portion of the ADC.
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Specification