Multi-level cell access buffer with dual function

• US 7,577,029 B2
• Filed: 12/28/2007
• Issued: 08/18/2009
• Est. Priority Date: 05/04/2007
• Status: Expired due to Fees

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Pyeon, Hong Beom
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US11/966,152
• Publication Number:
  US 20080273386A1
• Time in Patent Office: 599 Days
• Field of Search: 365/156
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement

Abstract

An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.

Claims

1. An access buffer for writing to a non-volatile memory, the access buffer comprising:

a single-ended input for receiving a single-ended input signal having an input bit to be written to the memory;

a first latch for latching the input bit, the first latch having a double-ended input for receiving a double-ended input signal containing the input bit;

a second latch for latching a value read from a lower page of a memory location of the non-volatile memory; and

a complement signal producer for producing a complement of the single-ended input signal, the double-ended input signal comprising the complement of the single-ended input signal and the single-ended input signal.

2. The access buffer of claim 1 wherein:

the access buffer has a first mode of operation in which the complement signal producer is producing the complement of the single-ended input signal and has a second mode of operation in which the second latch is functioning as a latch;

wherein the access buffer operates in the first mode of operation while receiving the input bit and latches the input bit into the first latch, and operates in the second mode of operation during multi-level cell programming.

3. The access buffer of claim 2 further comprising a driving inverter that forms part of both the second latch and the complement signal producer, the second latch further including a feedback data holder, the driving inverter and the feedback data holder being connected in a latch configuration.

4. The access buffer of claim 3 wherein:

the feedback data holder comprises a PMOS transistor, and

the driving inverter has an input connected to a drain of the transistor, the transistor having a gate connected to an output of the driving inverter, wherein the transistor holds data high so as to avoid interference with the driving inverter while the access buffer is operating in the first mode of operation.

5. The access buffer of claim 4 further comprising:

a pre-charging PMOS transistor for pre-charging the input of the driving inverter.

6. The access buffer of claim 2 wherein the complement signal producer comprises:

a first signal passer for passing the single-ended input signal to the driving inverter while the access buffer is in the first mode of operation, and that prevents passage of the input signal to the driving inverter while the access buffer is in the second mode of operation;

a second signal passer for passing the output of the driving inverter as one end of the double-ended input signal to the first latch while the access buffer is in the first mode of operation, and that prevents passage of the output of the driving inverter as one end of the double-ended input signal to the first latch while the access buffer is in the second mode of operation.

7. The access buffer of claim 6 further comprising:

a third signal passer for passing the output of the memory to the input of the second latch circuit while the access buffer is in the second mode, and that does not affect the output of the memory while the access buffer is in the first mode.

8. The access buffer of claim 7 wherein each of the first, second and third pass circuits comprise a respective NMOS transistor.

9. The access buffer of claim 8 wherein a drain of the NMOS transistor is connected to receive the input from the memory, and a gate the NMOS transistor is connected to the input of the second latch.

10. The access buffer of claim 8 wherein the non-volatile memory comprises a flash memory, the flash memory having a page buffer as the access buffer.

11. A method for writing to a non-volatile memory, the method comprising:

receiving a single-ended input signal having an input bit to be written to the memory;

producing a complement of the single-ended input signal using an input inverter comprising a driving inverter, the complement of the single-ended input signal and the single-ended input signal in combination forming a double-ended input signal;

latching the input bit into a first latch having a double-ended input for receiving a double-ended input signal containing the input bit; and

latching a value read from a lower page of a memory location of the non-volatile memory into a second latch comprising the driving inverter.

12. The method of claim 11 further comprising:

while receiving the input bit and latches the input bit into the first latch, operating the access buffer in a first mode of operation in which the input inverter is producing the complement of the single-ended input signal; and

during multi-level cell programming, operating the access buffer in a second mode of operation in which the second latch is functioning as a latch.

13. The method of claim 12 further comprising pre-charging an input of the driving inverter.

14. The method of claim 13 further comprising:

passing the output of the memory to the input of the second latch circuit while the access buffer is in the second mode.

15. The method of claim 12 further comprising:

passing the single-ended input signal to the driving inverter while the access buffer is in the first mode of operation, and preventing passage of the input signal to the driving inverter while the access buffer is in the second mode of operation;

passing the output of the driving inverter as one end of the double-ended input signal to the first latch while the access buffer is in the first mode of operation, and preventing passage of the output of the driving inverter as one end of the double-ended input signal to the first latch while the access buffer is in the second mode of operation.

16. A memory system having an access buffer for writing to a non-volatile memory structure, the access buffer comprising:

a single-ended input for receiving a single-ended input signal having an input bit to be written to the memory structure;

a first latch for latching the input bit, the first latch having a double-ended input for receiving a double-ended input signal containing the input bit;

a second latch for latching a value read from a lower page of a memory location of the non-volatile memory structure; and

a complement signal producer for producing a complement of the single-ended input signal, the double-ended input signal comprising the complement of the single-ended input signal and the single-ended input signal.

17. The memory system of claim 16 wherein the non-volatile memory structure comprises a memory cell array.

18. The memory system of claim 17 wherein the memory cell array comprises a flash memory cell string including a plurality of floating gate memory cells connected in-series, the series connected memory cells being coupled to a bitline, the memory cells being coupled to respective wordlines.

19. The memory system of claim 16 wherein the non-volatile memory comprises a flash memory, the flash memory having a page buffer as the access buffer.