Use of data latches in cache operations of non-volatile memories

• US 7,577,037 B2
• Filed: 01/03/2007
• Issued: 08/18/2009
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Li, Yan, Yero, Emilio
• Primary Examiner(s): Hoang; Huan
• Application Number:
  US11/619,513
• Publication Number:
  US 20070109867A1
• Time in Patent Office: 958 Days
• Field of Search: 365/185.22, 365/185.19, 365/185.03
• US Class Current: 365/185.22
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

Claims

1. A non-volatile memory device, including:

an array of memory cells, each capable of storing at least N bits of data, where N is an integer greater than one; and

a set of read/write circuits connected to the array for operating on a group of memory cells of said array in parallel, each read/write circuit having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells,

wherein, in a write process, the read/write circuits can store a first, N-bit set of data for a first group of memory cells in N data latches in each of the corresponding sets of data latches and write the first set of data into said first group of memory cells, wherein the writing includes alternating program and verify phases, and wherein once the group of memory cells have been programmed past one or more but less than all of the verify levels, one or more of the N data latches in each of the corresponding groups of data latches is released prior to completing said writing, and

wherein the read/write circuits can transfer a second set of data into the released data latches prior to completing said writing.

2. The non-volatile memory device of claim 1, wherein said second set of data is for a second group of memory cells of the array upon which the set of read/write circuits is able to operate, wherein the second group of memory cells is different from the first group of memory cells.

3. The non-volatile memory device of claim 1, said transfer of a second set of data into the released data latches includes reading said second set of data from said second group of memory cells into the released latches, wherein said read is performed between pulses of said writing.

4. The non-volatile memory device of claim 1, said transfer of a second set of data into the released data latches includes transferring out said second set of data from the released latches, wherein said transferring is begun prior to completing said writing.