Data input/output multiplexer of semiconductor device

• US 7,577,038 B2
• Filed: 09/29/2006
• Issued: 08/18/2009
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Shin, Beom-Ju
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US11/529,286
• Publication Number:
  US 20070070712A1
• Time in Patent Office: 1,054 Days
• Field of Search: 365/189.02, 365/191
• US Class Current: 365/189.02
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.

Claims

1. A semiconductor memory device, comprising:

a first data pad group for receiving data according to a first data input/output operation mode, a second data input/output operation mode and a third data input/output operation mode;

a second data pad group for receiving data according to the second data input/output operation mode and the third data input/output operation mode;

a third data pad group for receiving data according to the third data input/output operation mode;

a fourth data pad group for receiving data according to the third data input/output operation mode;

a first to a fourth data transferring line wherein each of the data transferring lines corresponds to a plurality of memory cells;

a first multiplexing unit for receiving a first input data from the first data pad group to transfer the first input data into one of the first data transferring line and the third data transferring line;

a second multiplexing unit for receiving a second input data from the second data pad group to transfer the second input data into one of the second data transferring line and the fourth data transferring line;

a first data transferring unit for receiving a third input data from the third data pad group to transfer the received third input data to the third data transferring line;

a second data transferring unit for receiving a fourth input data from the fourth data pad group to transfer the received fourth input data to the fourth data transferring line;

a third multiplexing unit for transferring data on one of the first data transferring line and the second data transferring line; and

a fourth multiplexing unit for transferring data on one of the third data transferring line and the fourth data transferring line.

2. The semiconductor memory device of claim 1, further comprising:

a first writing data transferring unit for receiving data on the first data transferring line to transfer the received data into corresponding memory cells;

a second writing data transferring unit for receiving data from the third multiplexing unit to transfer the received data into corresponding memory cells;

a third writing data transferring unit for receiving data on the third data transferring line to transfer the received data into corresponding memory cells; and

a fourth writing data transferring unit for receiving data from the third multiplexing unit to transfer the received data into corresponding memory cells.

3. The semiconductor memory device of claim 1, wherein the first data input/output operation mode is X4, the second data input/output operation mode is X8 and the third data input/output operation mode is 16 wherein the X4 is a data input/output mode for receiving 4 bit data at one data access command, the X8 is a data input/output mode for receiving 8 bit data at one data access command and the X16 is a data input/output mode for receiving 16 bit data at one data access command.

4. A semiconductor memory device, comprising:

a first reading data transferring unit for receiving data from corresponding memory cells according to a first data output operation mode, a second data output operation mode and a third data output operation mode;

a second reading data transferring unit for receiving data from corresponding memory cells according to the second data output operation mode and the third data output operation mode;

a third reading data transferring unit for receiving data from corresponding memory cells according to the third data output operation mode;

a fourth reading data transferring unit for receiving data from corresponding memory cells according to the third data output operation mode;

a first to a fourth data transferring line wherein each of the data transferring lines corresponds to a plurality of memory cells;

a first output data transferring unit for receiving a first output data from the first reading data transferring unit to transfer the first output data into the first data transferring line;

a second output data transferring unit for receiving a second output data from the second reading data transferring unit to transfer the second output data into the second data transferring line;

a first output data multiplexing unit for receiving a third output data from the third reading data transferring unit to transfer the third output data to one of the first data transferring line and the third data transferring line;

a second output data multiplexing unit for receiving a fourth output data from the third reading data transferring unit to transfer the fourth output data to one of the second data transferring line and the fourth data transferring line; and

a third output data multiplexing unit for transferring data on one of the first data transferring line and the second data transferring line.

5. The semiconductor memory device of claim 4, further comprising:

a first data pad group for receiving data from the third data multiplexing unit to transfer the received data into an external;

a second data pad group for receiving data on the second data transferring line to transfer the received data into the external;

a third data pad group for receiving data on the third data transferring line to transfer the received data into the external; and

a fourth data pad group for receiving data on the fourth data transferring line to transfer the received data into the external.

6. The semiconductor memory device of claim 4, wherein the first data output operation mode is X4, the second data output operation mode is X8 and the third data output operation mode is X16, wherein the X4 is a data output mode for receiving 4 bit data at one data access command, the X8 is a data output mode for receiving 8 bit data at one data access command and the X16 is a data output mode for receiving 16 bit data at one data access command.