Error detection on programmable logic resources

• US 7,577,055 B2
• Filed: 10/31/2007
• Issued: 08/18/2009
• Est. Priority Date: 10/11/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ngo, Ninh D., Lee, Andy L., Veenstra, Kerry
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/930,739
• Publication Number:
  US 20080052569A1
• Time in Patent Office: 657 Days
• Field of Search: 365/230.01, 365/230.08, 365/189.05
• US Class Current: 365/230.08
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Claims

1. Circuitry for accessing configuration data stored on a logic device and sending the configuration data to an output, comprising:

a memory in which the configuration data is

stored, wherein the memory comprises frames of memory cells;

an address register capable of storing a number of bits at least equal to a number of the frames, wherein each bit stored in the address register is associated with a different frame of the frames of memory cells;

a data register coupled to the memory; and

control logic coupled to the memory, the address register, and the data register to access a particular frame of memory cells, wherein the control logic asserts a bit in the address register associated with the particular frame of memory cells, causes data from the particular frame of memory cells to be loaded into the data register, and causes a subset of data from the particular frame of memory cells to be loaded from the data register to the output.

2. The circuitry of claim 1 wherein the memory is random access memory.

3. The circuitry of claim 1 wherein the memory is arranged in an array comprising rows and columns of memory cells.

4. The circuitry of claim 3 wherein each frame of memory cells comprises a column of memory cells.

5. The circuitry of claim 3 wherein each memory cell in a row is coupled to a data line associated with that row that is input to the data register.

6. The circuitry of claim 5 wherein each data line is precharged to a predetermined voltage when data is to be read from the memory.

7. The circuitry of claim 6 wherein the data from the particular frame of memory cells is read onto the data lines and loaded into the data register.

8. The circuitry of claim 1 wherein the control logic sets an address line coupled to the particular frame of memory cells to enable data from the particular frame of memory cells to be loaded into the data register.

9. The circuitry of claim 1 wherein the control logic:

deasserts the bit in the address register associated with the particular frame of memory cells; and

asserts a next bit in the address register associated with a next frame of memory cells while the subset of the data from the particular frame of memory cells is being loaded from the data register to the output.

10. The circuitry of claim 9 wherein the control logic further:

enables remaining subsets of the data from the particular frame of memory cells to be loaded from the data register to the output over subsequent clock cycles.

11. The circuitry of claim 10 wherein the control logic further:

sets a next address line coupled to the next frame of memory cells to enable data from the next frame of memory cells to be loaded into the data register when a last subset of the data from the particular frame of memory cells is being loaded from the data register to the output.

12. The circuitry of claim 1 wherein the control logic is a finite state machine.

13. The circuitry of claim 1 wherein the output is coupled to an error detection circuit.

14. Control logic that controls the communication of configuration data stored in a memory to an output circuitry, wherein the memory comprises frames of memory cells, the control logic being coupled to:

the memory;

an address register in which each bit location is associated with a distinct frame of the frames of memory cells; and

a data register that is further coupled to the memory, wherein the control logic;

a. asserts a bit in the address register to indicate a selection of a particular frame of memory cells,

b. loads the particular frame of memory cells to the data register,

c. loads the particular frame of memory cells in the data register to the output circuitry, wherein the particular frame of memory cells is loaded to the output circuitry one portion per clock cycle at a time, and

d. repeats a-c for each frame of the frames of memory cells.

15. The control logic of claim 14 wherein the control logic also precharges each data line associated with a row of memory cells in the memory that is input to the data register when data is to be read from the memory.

16. The control logic of claim 15 wherein the particular frame of memory cells is read onto the data lines and loaded into the data register.

17. The control logic of claim 14 wherein the control logic also sets an address line coupled to the particular frame of memory cells in enable the particular frame of memory cells to be loaded into the data register.

18. The control logic of claim 14 wherein the control logic also:

deasserts the bit in the address register associated with the particular frame of memory cells; and

asserts a next bit in the address register associated with a next frame of memory cells while the portion of the particular frame of memory cells is being loaded to the output circuitry.

19. The control logic of claim 18 wherein the control logic further:

sets a next address line coupled to the next frame of memory cells to enable the next frame of memory cells to be loaded into the data register when a last portion of the particular frame of memory cells is being loaded to the output circuitry.

20. The control logic of claim 14 wherein the control logic is a finite state machine.

21. The control logic of claim 14 wherein the output circuitry is error detection circuitry.

22. Method for accessing configuration data stored on a logic device and sending the configuration data to an output using control logic, comprising:

asserting a bit in an eddress register associated with a particular frame of memory cells in a memory in which the configuration data is stored;

loading data from the particular frame of memory cells into a data register; and

loading a subset of the data from the particular frame of memory cells from the data register to the output.

23. The method of claim 22 further comprising associating each bit in the address register with a different frame of memory cells in the memory.

24. The method of claim 23 further comprising deasserting bits other than the bit in the address register associated with the particular frame of memory cells in the memory.

25. The method of claim 22 wherein loading data from the particular frame of memory cells into the data register comprises precharging data lines that extend across each row of memory cells in the memory and that is input to the data register.

26. The method of claim 25 further comprising reading the data from the particular frame of memory cells onto the data lines.

27. The method of claim 22 further comprising setting an address line coupled to the particular frame of memory cells to enable the data from the particular frame of memory cells to be loaded into the data register.

28. The method of claim 22 wherein loading the subset of the data from the particular frame of memory cells further comprises:

deasserting the bit in the address register associated with the particular frame of memory cells;

asserting a next bit in the address register associated with a next frame of memory cells.

29. The method of claim 28 further comprising:

loading remaining subsets of the data from the particular frame of memory cells from the data register to the output over subsequent clock cycles.

30. The method of claim 29 wherein loading a last subset of the data from the particular frame of memory cells further comprises:

setting a next address line coupled to the next frame of memory cells to enable data from the next frame of memory cells to be loaded into the data register.