Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes
First Claim
1. A method for supporting bit labeling, the method comprising:
- receiving, at a receiver, a set of encoded bits of a binary Low Density Parity Check (LDPC) codeword, wherein the codeword has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code;
storing the set of encoded bits on a column by column basis; and
outputting the encoded bits on a row by row basis for mapping to a signal constellation.
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Abstract
An approach is provided for bit labeling of a signal constellation. A transmitter generates encoded signals using, according to one embodiment, a structured parity check matrix of a Low Density Parity Check (LDPC) code. The transmitter includes an encoder for transforming an input message into a codeword represented by a plurality of set of bits. The transmitter includes logic for mapping non-sequentially (e.g., interleaving) one set of bits into a higher order constellation (Quadrature Phase Shift Keying (QPSK), 8-PSK, 16-APSK (Amplitude Phase Shift Keying), 32-APSK, etc.), wherein a symbol of the higher order constellation corresponding to the one set of bits is output based on the mapping.
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Citations
25 Claims
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1. A method for supporting bit labeling, the method comprising:
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receiving, at a receiver, a set of encoded bits of a binary Low Density Parity Check (LDPC) codeword, wherein the codeword has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code; storing the set of encoded bits on a column by column basis; and outputting the encoded bits on a row by row basis for mapping to a signal constellation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A mapper for supporting bit labeling, the mapper comprising:
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means for receiving a set of encoded bits of a binary Low Density Parity Check (LDPC) codeword, wherein the codeword has a parity check matrix with structure that provides contiguous storage of edge values for decoding of the LDPC code; means for storing the set of encoded bits on a column by column basis; and means for outputting the encoded bits on a row by row basis for a non-sequential read operation, wherein the output encoded bits are mapped to a signal constellation. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. An apparatus comprising:
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means for receiving one of a plurality of set of bits of a codeword from a binary Low Density Parity Check (LDPC) encoder for transforming an input message into the codeword, wherein the codeword has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code; means for writing N encoded bits to a block interleaver on a column by column basis, N being an integer; means for reading out the encoded bits on a row by row basis; means for mapping the read out encoded bits into a higher order constellation; and means for outputting a symbol of the higher order constellation corresponding to the one set of bits based on the mapping for transmission over an Additive White Gaussian Noise (AWGN) channel. - View Dependent Claims (19)
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20. An apparatus comprising:
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means for demodulating a received Low Density Parity Check (LDPC) encoded signal, over an Additive White Gaussian Noise (AWGN) channel, representing a codeword having a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code, wherein the encoded signal being modulated according to a non-sequential mapping, based on the structure of the codeword, of a plurality of bits corresponding to the codeword, wherein the N encoded bits are written to a block interleaver column by column and read out row by row; and means for decoding the codeword associated with the encoded signal. - View Dependent Claims (21)
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22. A method comprising:
decoding a Low Density Parity Check (LDPC) encoded signal, wherein the signal was modulated according to a non-sequential mapping of a plurality of bits, corresponding to a codeword represented by the signal, to a signal constellation by writing the encoded bits to a block interleaver column by column and read out row by row, the codeword having a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code. - View Dependent Claims (23)
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24. A decoder comprising:
logic configured to decode a Low Density Parity Check (LDPC) encoded signal, wherein the signal was modulated according to a non-sequential mapping of a plurality of bits, corresponding to a codeword represented by the signal, to a signal constellation by writing the encoded bits to a block interleaver column by column and read out row by row, the codeword having a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code. - View Dependent Claims (25)
Specification