Multiplexed RF isolator circuit

• US 7,577,223 B2
• Filed: 06/30/2007
• Issued: 08/18/2009
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Alfano, Donald E., Dupuis, Timothy, Etter, Brett
• Primary Examiner(s): Ahn; Sam K
• Application Number:
  US11/772,186
• Publication Number:
  US 20080025450A1
• Time in Patent Office: 780 Days
• Field of Search: 375/222, 375/241, 375/242, 375/340, 375/362, 379/93.05, 379/93.29, 379/90.01, 379/93.28, 379/93.31
• US Class Current: 375/362
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/1204 : Optical Diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/33523 : with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H04B 2203/542 : using zero crossing information
• CPC Class Codes: H04B 3/542 : the information being in digital form
• CPC Class Codes: H04B 3/56 : Circuits for coupling, blocking, or by-passing of signals
• CPC Class Codes: H04L 25/0266 : Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

An integrated circuit isolator for providing data transfer of digital data signals across a voltage isolation barrier includes an integrated circuit package having a first plurality of input data pins on one side of the isolation barrier and a corresponding plurality of output data pins on the other side of the isolation boundary. First circuitry is associated with the first plurality of input data pins and second circuitry is associated with the plurality of output data pins. A communications interface provides across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel for communicating synchronization clock data from the first circuitry to the second circuitry. The first circuitry is operable to communicate information from input digital data overlapping each other in time and received on two or more of the associated first plurality of input data pins across the first communications channel and to communicate the synchronization clock signal across the second communications channel. The second circuitry is operable to receive the communicated data from the first circuitry and reconstruct the data for output on the ones of the plurality of output data pins corresponding to the two or more of the associated plurality of input data pins from which the data was communicated responsive to the synchronization clock signal.

Claims

1. An integrated circuit isolator for providing data transfer of digital data signals across a voltage isolation barrier, comprising:

an integrated circuit package having a first plurality of input data pins on one side of the isolation barrier and a corresponding plurality of output data pins on the other side of the isolation boundary;

first circuitry associated with the first plurality of input data pins and second circuitry associated with the plurality of output data pins;

a communications interface for providing across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel for communicating synchronization clock data from the first circuitry to the second circuitry, wherein the communications interface comprises a first transformer for providing the first communications channel and a second transformer for providing the second communications channel and the first circuitry having communications circuitry associated therewith for transmitting data to the first transformer and to the second transformer and the second circuitry having communications circuitry for receiving data from the first transformer and the second transformer; and

the first circuitry operable to communicate information from input digital data overlapping each other in time and received on two or more of the associated first plurality of input data pins across the first communications channel and to communicate the synchronization clock signal across the second communications channel and the second circuitry operable to receive the communicated data from the first circuitry and reconstruct the data for output on the ones of the plurality of output data pins corresponding to the two or more of the associated plurality of input data pins from which the data was communicated responsive to the synchronization clock signal.

2. The isolator of claim 1, wherein:

the first circuitry includes a time multiplexer to time multiplex input digital data signals and transmit the time multiplexed input digital data signals across the first transformer; and

the second circuitry includes a time demultiplexer for receiving from the first transformer the multiplexed input digital data signals and demultiplexing as a reconstructed sample of the respective digital data output signals and a latch for latching the reconstructed sample onto the plurality of output data pins.

3. The isolator of claim 2, wherein the first circuitry is disposed within the package on a first integrated circuit and the second circuitry is disposed within the package on a second integrated circuit and voltage isolated from the first integrated circuit, the first and second transformers separating the first and second integrated circuits.

4. The isolator of claim 3, wherein for the first circuitry:

wherein the time multiplexer comprises;

a sampling circuit for sequentially sampling received input digital data signals from the plurality of digital data input pins into defined time slots during a sampling frame, and

a transmitter for transmitting in a serial format the sampled input digital data signals to the first transformer; and

wherein the demultiplexer comprises;

a receiver for receiving from the first transformer the serially transmitted sampled input digital data signals, and

a demultiplexer for demultiplexing the received sampled input digital data signals to provide the plurality of output digital data signals for interface to the plurality of digital data output pins.

5. The isolator of claim 2, wherein the time multiplexer include a radio frequency (RF) transmitter for driving the first and second transformers with an RF signal encoded with the time multiplexed input digital data signals and synchronization clock signal in accordance with a serial digital data protocol, and the time demultiplexers include an RF receiver for receiving the RF signal from the other side of the first and second transformers.

6. An integrated circuit isolator providing for communications of multiple digital data signals over a pair of common communications channels across a voltage isolation barrier, comprising:

an integrated circuit package having a plurality of input pins for receiving respective ones of a plurality of digital data signals on one side of the isolation barrier and a plurality of output pins for outputting a plurality of respective output digital data signals on the other side of the isolation barrier;

first circuitry disposed within the package and on the one side of the isolation barrier and including;

a serializer for receiving the plurality of digital data signals and outputting a serial data stream;

a multiplexer for multiplexing a staff bit onto a beginning of the serial data stream on a first common communications channel and for placing a synchronization clock signal onto a second common communications channel;

second circuitry disposed within the package and on the other side of the isolation barrier and including;

a demultiplexer for removing the staff bit from the beginning of the serial data stream and separately outputting the serial data stream and the synchronization clock signal;

a deserializer for receiving the serial data stream and outputting the plurality of digital data signals in parallel; and

a communications interface for providing the first common communications channel and the second common communications channel, such that voltage isolation is maintained between the first an the second circuitry within the package.

7. The integrated circuit isolator of claim 6, wherein the first circuitry further includes:

a sync generator for generating the synchronization clock signal and for generating the start data bit responsive to a first control signal;

a first state machine for generating the first control signal.

8. The integrated circuit isolator of claim 7, wherein the sync generator farther generates the start bit to indicate a beginning of a data frame.

9. The integrated circuit isolator of claim 8, wherein sync generator generates the start bit while synchronization clock signal is high and the serial data stream is high.

10. The integrated circuit isolator of claim 7, wherein the first state machine generates a second control signal to latch the received plurality of parallel digital inputs onto the plurality of inputs of the serializer.

11. The integrated circuit isolator of claim 6, wherein the second circuitry further includes:

a sync detector connected to the first common communications channel and the second common communications channel, the sync detector detecting the start bit indicating a beginning of the serial data stream and generating a detect staff frame signal responsive thereto;

a second state machine for providing a third control signal to the demultiplexer responsive to detection of the detect start frame signal.

12. The integrated circuit isolator of claim 11, wherein the sync detector generates the detect start frame signal to the second state machine responsive to detection of a signal going high on the first common communications channel while the synchronization clock signal is high.

13. The integrated circuit isolator of claim 11, further including a Measure-Controlled Delay (MCD) circuit connected to the second common communications channel, the MCD generating an MCD control signal to the second state machine responsive to detection of failure of the synchronization clock signal on the second common communications channel.

14. The integrated circuit isolator of claim 11, wherein the second state machine generates a latch signal to latch the outputs of the de-serializer responsive to receipt of a final bit of the plurality of digital data inputs in the serial data stream.

15. The integrated circuit isolator of claim 11, wherein the second state machine generates a clear signal responsive to detection of a start bit on the first common communications channel.

16. An integrated circuit isolator providing for communications of multiple digital data signals over a pair of common communications channels across a voltage isolation barrier, comprising:

an integrated circuit package having a plurality of input pins for receiving respective ones of a plurality of digital data signals on one side of the isolation barrier and a plurality of output pins for outputting a plurality of respective output digital data signals on the other side of the isolation barrier;

first circuitry disposed within the package and on the one side of the isolation barrier and including;

a serializer for receiving the plurality of digital data signals and outputting a serial data stream;

a multiplexer for multiplexing a start bit onto a beginning of the serial data stream on a first common communications channel and for placing a synchronization clock signal onto a second common communications channel;

a sync generator for generating the synchronization clock signal and for generating the start data bit responsive to a first control signal to indicate a beginning of a data frame;

a first state machine for generating the first control signal;

second circuitry disposed within the package and on the other side of the isolation barrier and including;

a demultiplexer for removing the start bit from the beginning of the serial data stream and separately outputting the serial data stream and the synchronization clock signal;

a deserializer for receiving the serial data stream and outputting the plurality of digital data signals in parallel;

a sync detector connected to the first common communications channel and the second common communications channel, the sync detector detecting the start bit indicating a beginning of the serial data stream and generating a detect start frame signal responsive thereto;

a second state machine for providing a third control signal to the demultiplexer responsive to detection of the detect start frame signal

a communications interface for providing the first common communications channel and the second common communications channel, such that voltage isolation is maintained between the first an the second circuitry within the package.

17. The integrated circuit isolator of claim 16, wherein sync generator generates the start bit while synchronization clock signal is high and the serial data stream is high.

18. The integrated circuit isolator of claim 16, wherein the first state machine generates a second control signal to latch the received plurality of parallel digital inputs onto the plurality of inputs of the serializer.

19. The integrated circuit isolator of claim 16, wherein the sync detector generates the detect start frame signal to the second state machine responsive to detection of a signal going high on the first common communications channel while the synchronization clock signal is high.

20. The integrated circuit isolator of claim 16, further including an MCD circuit connected to the second common communications channel, the MCD generating an MCD control signal to the second state machine responsive to detection of failure of the synchronization clock signal on the second common communications channel.

21. The integrated circuit isolator of claim 16, wherein the second state machine generates a latch signal to latch the outputs of the de-serializer responsive to receipt of a final bit of the plurality of digital data inputs in the serial data stream.

22. The integrated circuit isolator of claim 16, wherein the second state machine generates a clear signal responsive to detection of a start bit on the first common communications channel.

23. A method for providing communications of multiple digital data signals over a pair of common communications channels across a voltage isolation barrier, comprising the steps of:

receiving on one side of the voltage isolation barrier a plurality of digital data signals on respective ones of a plurality of input pins of an integrated circuit package;

converting the received plurality of digital data signals into a serial data stream;

multiplexing a start bit onto a beginning of the serial data stream;

transmitting the serial data stream with the start bit on a first common communications channel across the voltage isolation barrier;

transmitting a synchronization clock signal onto a second common communications channel across the voltage isolation barrier;

receiving the serial data stream with the start bit on the first common communications channel on the other side of the voltage isolation barrier;

receiving the synchronization clock signal on the second common communications channel on the other side of the voltage isolation barrier;

removing the start bit from the beginning of the serial data stream;

converting the serial data stream into the plurality of digital data signals responsive to the synchronization clock signal;

outputting on an other side of the voltage isolation barrier the plurality of digital data signals on respective ones of a plurality of output pins of the integrated circuit package.

24. The method of claim 23, further including the steps of:

generating a first control signal at a state machine; and

generating the synchronization clock signal and generating the start data bit responsive to a first control signal.

25. The method of claim 24, wherein the step of generating the start bit further includes the step of generating the start bit to indicate a beginning of a data frame.

26. The method of claim 24, wherein the step of generating the start bit further includes the step of generating the start bit while the synchronization clock signal is high and the serial data stream is high.

27. The method of claim 23, further including step of generating a second control signal to latch the received plurality of parallel digital inputs to a constant value.

28. The method of claim 23, wherein the step of removing the start bit further includes the steps of:

monitoring the first common communications channel and the second common communications channel;

detecting the start bit indicating a beginning of the serial data stream;

generating a detect start frame signal responsive thereto; and

removing the start bit from the beginning of the serial data stream, responsive to the detect start frame signal.

29. The method of claim 28, wherein the step of detecting the start bit further includes the step of detecting the start bit indicating the beginning of the serial data stream responsive to detection of a signal going high on the first common communications channel while the synchronization clock signal is high on the second common communications channel.

30. The method of claim 23, further including the steps of:

monitoring the second common communications channel; and

generating an clock failure control signal responsive to detection of failure of the synchronization clock signal on the second common communications channel.

31. The method of claim 23, wherein the step of converting the serial data stream further includes the step of generating a latch signal to latch the outputs of the de-serializer responsive to receipt of a final bit of the plurality of digital data inputs in the serial data stream.

32. The method of step of generating a clear signal responsive to detection of the start bit on the first common communications channel.