Upgradable memory system with reconfigurable interconnect

• US 7,577,789 B2
• Filed: 03/24/2006
• Issued: 08/18/2009
• Est. Priority Date: 02/28/2001
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): Shah; Sanjiv
• Assistant Examiner(s): Rojas; Midys
• Application Number:
  US11/388,449
• Publication Number:
  US 20060236031A1
• Time in Patent Office: 1,243 Days
• Field of Search: None
• US Class Current: 711/115
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H05K 1/117 Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 1/14 Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 2201/09954 More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
• CPC Class Codes: H05K 2201/10189 Non-printed connector
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Claims

1. A system comprising:

a. a motherboard including;

i. a first electrical receptacle;

ii. a first set of signal lines coupled to the first electrical receptacle;

iii. a second electrical receptacle; and

iv. a second set of signal lines coupled to the second electrical receptacle; and

b. at least one of a first logic module and a second logic module;

c. the motherboard supporting multiple data-width configurations, including;

i. a single-module configuration in which the first logic module is inserted into the first electrical receptacle and the second electrical receptacle lacks the second logic module, wherein the first logic module is coupled, via the first electrical receptacle, to the first and second sets of signal lines and is receiving first data of a first data width transferred to the first electrical receptacle via both the first set of signal lines and the second set of signal lines; and

ii. a dual-module configuration in which the first logic module is inserted into the first electrical receptacle and the second logic module is inserted into the second electrical receptacle, wherein the first logic module is coupled, via the first electrical receptacle, to the first set of signal lines and is receiving second data of a second data width narrower than the first data width and transferred to the first electrical receptacle via the first set of signal lines, and wherein the second logic module is coupled, via the second electrical receptacle, to the second set of signal lines and is receiving third data transferred to the second electrical receptacle via the second set of signal lines;

wherein in the dual-module configuration the first logic module is decoupled from the second set of signal lines and does not receive data via the second set of signal lines.

2. The system of claim 1, wherein the first and second logic modules are memory modules.

3. The system of claim 1, further comprising a third set of signal lines disposed between the second set of signal lines and the first electrical receptacle in the single-module configuration and disconnected from the second set of signal lines in the dual-module configuration.

4. The system of claim 3, wherein the first, second, and third sets of signal lines are traces on the motherboard.

5. The system of claim 1, wherein the first data width is twice the second data width.

6. The system of claim 1, wherein the first logic module includes a module backplane supporting opposed rows of electrical contacts, wherein a first set of the electrical contacts is coupled to the first set of signal lines in the single-module and the dual-module configurations, and wherein a second set of electrical contacts is coupled to the second set of signal lines in the single-module configuration and is decoupled from the second set of signal lines in the dual-module configuration.

7. The system of claim 1, further comprising a shorting module inserted into the second electrical receptacle in the single-module configuration.

8. The system of claim 1, wherein the first logic module includes programmable state storage adapted to select among the first data width and the second data width.

9. The system of claim 1, wherein at least one of the first and second logic modules includes a means for programming the logic module to support the first data width or the second data width.

10. The system of claim 1, further comprising a controller coupled to the first and second sets of signal lines.

11. The system of claim 10, wherein the controller is coupled to the first logic module in the single-module configuration via the first and second sets of signal lines and is coupled to the first logic module via the first set of signal lines and the second logic module via the second set of signal lines in the dual-module configuration.

12. The system of claim 10, wherein the controller is coupled to the first logic module in the single-module configuration via the second electrical receptacle.

13. The system of claim 1, wherein the third data is of the second data width.

14. A system comprising:

a. at least one of a first module and a second module;

b. a motherboard supporting multiple data-width configurations and including;

i. first and second electrical receptacles adapted to receive the respective first and second modules;

ii. a first set of signal lines extending to the first electrical receptacle;

iii. a second set of signal lines extending to the second electrical receptacle;

iv. means for supporting a single-module configuration in which the first module is inserted into the first electrical receptacle and is coupled to the first and second sets of signal lines and is receiving first data of a first data width transferred to the first electrical receptacle via both the first and second sets of signal lines;

v. means for supporting a dual-module configuration in which the first module is inserted into the first electrical receptacle and the second module is inserted into the second electrical receptacle, wherein the first module is coupled to the first set of signal lines and is receiving second data of a second data width narrower than the first data width and transferred to the first electrical receptacle via the first set of signal lines and the second module is coupled to the second set of signal lines and is receiving third data transferred to the second electrical receptacle via the second set of signal lines; and

vi. a third set of signal lines coupled in series with the second set of signal lines in the single-module configuration and decoupled from the second set of signal lines in the dual-module configuration.

15. A system comprising:

a. at least one of a first module and a second module;

b. a motherboard supporting multiple data-width configurations and including;

i. first and second electrical receptacles adapted to receive the respective first and second modules;

ii. a first set of signal lines extending to the first electrical receptacle;

iii. a second set of signal lines extending to the second electrical receptacle;

iv. means for supporting a single-module configuration in which the first module is inserted into the first electrical receptacle and is coupled to the first and second sets of signal lines and is receiving first data of a first data width transferred to the first electrical receptacle via both the first and second sets of signal lines; and

v. means for supporting a dual-module configuration in which the first module is inserted into the first electrical receptacle and the second module is inserted into the second electrical receptacle, wherein the first module is coupled to the first set of signal lines and is receiving second data of a second data width narrower than the first data width and transferred to the first electrical receptacle via the first set of signal lines and the second module is coupled to the second set of signal lines and is receiving third data transferred to the second electrical receptacle via the second set of signal lines;

wherein the first module physically contacts the first connector and is electrically coupled to the second set of signal lines via the second connector in the single-module configuration and is decoupled from the second set of signal lines in the dual-module configuration.

16. A configurable memory system comprising:

a. a memory controller;

b. at least one electrical connector adapted to receive a plurality of memory modules, including a first memory module and a second memory module;

c. a first set of signal lines extending between the memory controller and the at least one electrical connector;

d. a second set of signal lines extending between the memory controller and the at least one electrical connector;

e. the memory system supporting a plurality of memory-width configurations, including;

i. a first memory configuration in which the first memory module is in physical contact with the at least one electrical connector and coupled to the memory controller via the first and second sets of signal lines to communicate data of a first data width with the memory controller; and

ii. a second memory configuration in which the first memory module is in physical contact with the at least one electrical connector and coupled to the memory controller via the first set of signal lines and decoupled from the second set of signal lines and the second memory module is in physical contact with the at least one electrical connector and coupled to the memory controller via the second set of signal lines to communicate data of a second data width narrower than the first data width with the memory controller and decoupled from the first set of signal lines.

17. The configurable memory system of claim 16, further comprising a third set of signal lines coupled in series with the second set of signal lines in the first memory configuration and decoupled from the second set of signal lines in the second memory configuration.

18. The configurable memory system of claim 16, wherein the at least one connector includes a first connector adapted to receive the first memory module and a second connector adapted to receive the second memory module.

19. The configurable memory system of claim 16, wherein the first memory module physically contacts the first connector and is electrically coupled to the second set of signal lines via the second connector in the first memory configuration.

20. The configurable memory system of claim 16, wherein the first memory module is of the first data width in the first configuration and of the second data width in the second configuration.

21. A configurable memory system comprising:

a. a memory controller;

b. at least one electrical connector adapted to receive a plurality of memory modules, including a first memory module and a second memory module;

c. a first set of signal lines extending between the memory controller and the at least one electrical connector;

d. a second set of signal lines extending between the memory controller and the at least one electrical connector;

e. the memory system supporting a plurality of memory-width configurations, including;

i. a first memory configuration in which the first memory module is in physical contact with the at least one electrical connector and coupled to the memory controller via the first and second sets of signal lines to communicate data of a first data width; and

ii. a second memory configuration in which the first memory module is in physical contact with the at least one electrical connector and coupled to the memory controller via the first set of signal lines and decoupled from the second set of signal lines to communicate data of a second data width narrower than the first data width and the second memory module is in physical contact with the at least one electrical connector and coupled to the memory controller via the second set of signal lines and decoupled from the first set of signal lines;

f. wherein the at least one connector is a single connector adapted to receive one or both of the first and second memory modules.

22. A system comprising:

a. a controller;

b. a first electrical receptacle coupled to the controller via a first set of signal lines;

c. a second electrical receptacle coupled to the controller via a second set of signal lines;

d. at least one of a first module and a second module, the first module including a first memory device having a variable data width, the second module including a second memory device;

e. the memory system supporting multiple data-width configurations, including;

i. a single-module configuration in which the first module is inserted into the first electrical receptacle and the second electrical receptacle lacks the second module, wherein the first module is coupled, via the first electrical receptacle, to the first and second sets of signal lines and the first memory device is configured to have a first data width and exchange data with the controller over the first and second sets of signal lines; and

ii. a dual-module configuration in which the first module is inserted into the first electrical receptacle and the second module is inserted into the second electrical receptacle, wherein the first module is coupled, via the first electrical receptacle, to the first set of signal lines and the first memory device is configured to have a second data width narrower than the first data width and exchange data with the controller over the first set of signal lines, and wherein the second memory device exchanges data with the controller over the second set of signal lines;

wherein the first memory device is decoupled from the second set of data lines in the dual-module configuration.

23. The motherboard of claim 22, wherein the second memory device exchanges data with the controller using the second data width.

24. The motherboard of claim 22, wherein the second memory device has a variable data width and is configured to have the second data width.

25. A system comprising:

a. at least one of a first module and a second module, the first module including a first memory device and supporting a variable data width, the second module including a second memory device; and

b. a motherboard that includes;

i. a controller;

ii. a first electrical receptacle coupled to the controller via a first set of signal lines; and

iii. a second electrical receptacle coupled to the controller via a second set of signal lines;

c. the motherboard supporting multiple data-width configurations, including;

i. a single-module configuration in which the first module is inserted into the first electrical receptacle and the second electrical receptacle lacks the second module, wherein the first module is coupled, via the first electrical receptacle, to the first and second sets of signal lines and is configured to have a first data width and to exchange data of the first data width between the first memory device and the controller over at least one of the first and second sets of signal lines; and

ii. a dual-module configuration in which the first module is inserted into the first electrical receptacle and the second module is inserted into the second electrical receptacle, wherein the first module is coupled, via the first electrical receptacle, to the first set of signal lines and is configured to have a second data width narrower than the first data width and to exchange data of the second data width between the second memory device and the controller over the first set of signal lines, and wherein the second memory module exchanges data with the controller over the second set of signal lines;

wherein the first memory device is decoupled from the second set of data lines in the dual-module configuration.

26. The motherboard of claim 25, wherein the second memory device exchanges data with the controller using the second data width.

27. The motherboard of claim 25, wherein the second memory device has a variable data width and is configured to have the second data width in the dual-module configuration.

28. The motherboard of claim 25, wherein the second memory device exchanges data with the controller using the second set of signal lines in the dual-module configuration.