Wake-up and sleep conditions of processors in a multi-processor system

• US 7,577,823 B2
• Filed: 06/23/2003
• Issued: 08/18/2009
• Est. Priority Date: 07/03/2002
• Status: Expired due to Fees

• Current Assignee: Commonwealth Research Group LLC
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Hoogerbrugge, Jan
• Primary Examiner(s): Kindred; Alford W
• Assistant Examiner(s): Geib; Benjamin P
• Application Number:
  US10/519,649
• Publication Number:
  US 20060069738A1
• Time in Patent Office: 2,248 Days
• Field of Search: 712/10, 712/203, 712/43
• US Class Current: 712/43
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 2209/5014 Reservation
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention relates to a multi-processor computer system comprising

• • at least two processors for parallel execution of processes,
  • at least two cache memory units, each being associated with and connected to a separate processor,
  • a connection bus connecting said processors and said cache memory units, and
  • a process list unit connected to said connection line for storing a process list of processes to be available for execution by said processors.

In order to enable power saving if no processes for execution are available while guaranteeing a fast wake-up procedure if such processes are available it is proposed according to the present invention that said processors are adapted for loading a global wake-up variable signalling process additions of processes to said process list into their associated cache memory unit, for switching into a low-power mode if said process list contains no process for execution by said processors and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list.

Thus, according to the present invention the cache coherence protocol is used for communicating and signalling the availability of processes for execution.

Claims

1. Multi-processor computer system comprising at least two processors (1) for parallel execution of processes, at least two cache memory units (2), each being associated with and connected to a separate processor (1) of the at least two processors, a connection bus (4) connecting said processors (1) and said cache memory units (2), and a process list unit (3) connected to said connection bus (4) for storing a process list of processes to be available for execution by said processors (1), wherein said processors (1) are adapted for loading a global wake-up variable signaling process additions of processes to said process list into their associated cache memory unit (2), for switching into a low-power mode if said process list contains no process for execution by said processors (1) and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list.

2. Multi-processor computer system as claimed in claim 1, wherein said processors (1) are adapted to switch into the normal-power mode if the wake-up variable held in the associated cache memory units (2) is changed due to an addition of a process to said process list.

3. Multi-processor computer system as claimed in claim 1, wherein said processors (1) are adapted to execute a store command on the wake-up variable when adding a process to said process list.

4. Multi-processor computer system as claimed in claim 1, wherein said processors (1) are adapted to send a request to other processors to drop the wake-up variable from their associated cache memory unit when adding a process to said process list.

5. Multi-processor computer system as claimed in claim 1, wherein said computer system is adapted for implementing an invalidation based cache coherence protocol.

6. Processor for use in a multi-processor computer system comprising at least two processors (1) for parallel execution of processes, at least two cache memory units (2), each being associated with and connected to a separate processor (1) of the at least two processors, a connection bus (4) connecting said processors (1) and said cache memory units (2), and a process list unit (3) connected to said connection bus (4) for storing a process list of processes to be available for execution by said processors (1), wherein a processor (1) of the at least two processors is adapted for loading a global wake-up variable signaling process additions of processes to said process list into its associated cache memory unit (2), for switching into a low-power mode if said process list contains no process for execution by said processor and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list.

7. Method of scheduling the execution of processes in a multi-processor computer system comprising at least two processors (1) for parallel execution of processes, at least two cache memory units (2), each being associated with and connected to a separate processor of the at least two processors (1), a connection bus (4) connecting said processors (1) and said cache memory units (2), and a process list unit (3) connected to said connection bus(4) for storing a process list of processes to be available for execution by said processors (1), said method comprising the steps of:

loading a global wake-up variable signaling process additions of processes to said process list by a processor (1) into its associated cache memory unit (2), adding a process to said process list, and changing the wake-up variable signaling said addition of a process to said process list thus causing said processor (1) to switch from a low-power mode into a normal-power mode.

8. Method of executing a process by a processor in a multi-processor computer system comprising at least two processors (1) for parallel execution of processes, at least two cache memory units (2), each being associated with and connected to a separate processor (1) of the at least two processors, a connection bus (4) connecting said processors (1) and said cache memory units (2), and a process list unit (3) connected to said connection bus (4) for storing a process list of processes to be available for execution by said processors (1), said method comprising the steps of:

loading a global wake-up variable signaling process additions of processes to said process list into an associated cache memory unit (2), switching into a low-power mode if said process list contains no process for execution by said processor (1), switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list, and accessing said process list to get said added process for execution.