Semiconductor device manufacturing method

• US 7,579,220 B2
• Filed: 05/16/2006
• Issued: 08/25/2009
• Est. Priority Date: 05/20/2005
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Osame, Mitsuaki, Ohnuma, Hideto, Yamazaki, Shunpei, Sakakura, Masayuki, Nagai, Masaharu, Komori, Shigeki
• Primary Examiner(s): Lee; Hsien-ming
• Application Number:
  US11/383,694
• Publication Number:
  US 20060261336A1
• Time in Patent Office: 1,197 Days
• Field of Search: 438/149, 438151-155, 438/162, 438/164
• US Class Current: 438/149
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays

Abstract

It is an object of the present invention to form a plurality of elements in a limited area to reduce the area occupied by the elements for integration so that further higher resolution (increase in number of pixels), reduction of each display pixel pitch with miniaturization, and integration of a driver circuit that drives a pixel portion can be advanced in semiconductor devices such as liquid crystal display devices and light-emitting devices that has EL elements. A photomask or a reticle provided with an assist pattern that is composed of a diffraction grating pattern or a semi-transparent film and has a function of reducing a light intensity is applied to a photolithography process for forming a gate electrode to form a complicated gate electrode. In addition, a top-gate TFT that has the multi-gate structure described above and a top gate TFT that has a single-gate structure can be formed on the same substrate just by changing the mask without increasing the number of processes.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating film on a semiconductor layer;

forming a first conductive film on the insulating film;

forming a second conductive film on the first conductive film;

forming a resist pattern on the second conductive film having end portions and a central portion that are thinner than remaining portions of the resist pattern from a cross-sectional view;

etching the second conductive film and the first conductive film to form a first conductive pattern from the first conductive film and a plurality of second conductive patterns from the second conductive film, the plurality of second conductive patterns being located apart from each other on the first conductive pattern;

doping the semiconductor layer with an impurity element by using the first conductive pattern and the plurality of second conductive patterns as masks to form a pair of first impurity regions in the semiconductor layer, both of the first impurity regions being located outside the first conductive pattern; and

doping the semiconductor layer with an impurity element by using the plurality of second conductive patterns as masks to form second impurity regions in the semiconductor layer, the second impurity regions being overlapped with the first conductive pattern.

2. The method for manufacturing the semiconductor device according to claim 1, wherein the width of the first conductive pattern is wider than the sum of the widths of the plurality of second conductive patterns.

3. The method for manufacturing the semiconductor device according to claim 1, wherein the resist pattern is formed by using a photomask or a reticle that has a diffraction grating pattern or a semi-transparent film.

4. The method for manufacturing the semiconductor device according to claim 1, wherein the first conductive pattern and the plurality of second conductive patterns serve as a gate electrode.

5. The method for manufacturing the semiconductor device according to claim 1, wherein the second impurity regions are LDD regions.

6. The method for manufacturing the semiconductor device according to claim 1, wherein the pair of first impurity regions are a source region and a drain region.

7. A method for manufacturing a semiconductor device comprising the steps of:

forming a first insulating film on a substrate;

forming a semiconductor layer on the first insulating film;

forming a second insulating film on a semiconductor layer;

forming a first conductive film on the second insulating film;

forming a second conductive film on the first conductive film;

forming a resist pattern on the second conductive film having end portions and a central portion that are thinner than remaining portions of the resist pattern from a cross-sectional view;

etching the second conductive film and the first conductive film to form a first conductive pattern from the first conductive film and a plurality of second conductive patterns from the second conductive film, the plurality of second conductive patterns being located apart from each other on the first conductive pattern;

doping the semiconductor layer with an impurity element by using the first conductive pattern and the plurality of second conductive patterns as masks to form a pair of first impurity regions in the semiconductor layer, both of the first impurity regions being located outside the first conductive pattern;

doping the semiconductor layer with an impurity element by using the plurality of second conductive patterns as masks to form second impurity regions in the semiconductor layer, the second impurity regions being overlapped with the first conductive pattern;

forming a third insulating film over the first conductive pattern and the plurality of second conductive patterns;

forming a source electrode and a drain electrode over the third insulating film; and

forming a pixel electrode connected to one of the source electrode and the drain electrode.

8. The method for manufacturing the semiconductor device according to claim 7, wherein the width of the first conductive pattern is wider than the sum of the widths of the plurality of second conductive patterns.

9. The method for manufacturing the semiconductor device according to claim 7, wherein the resist pattern is formed by using a photomask or a reticle that has a diffraction grating pattern or a semi-transparent film.

10. The method for manufacturing the semiconductor device according to claim 7, wherein the first conductive pattern and the plurality of second conductive patterns serve as a gate electrode.

11. The method for manufacturing the semiconductor device according to claim 7, wherein the second impurity regions are LDD regions.

12. The method for manufacturing the semiconductor device according to claim 7, wherein the pair of first impurity regions are a source region and a drain region.

13. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating film on a semiconductor layer;

forming a First conductive Film on the insulating film;

forming a second conductive film on the first conductive film;

forming a resist pattern on the second conductive film having a concave upper surface;

etching the second conductive film and the first conductive film to form a first conductive pattern from the first conductive film and a plurality of second conductive patterns from the second conductive film, the plurality of second conductive patterns being located apart from each other on the first conductive pattern;

doping the semiconductor layer with an impurity element by using the first conductive pattern and the plurality of second conductive patterns as masks to form a pair of first impurity regions in the semiconductor layer, both of the first impurity regions being located outside the first conductive pattern; and

doping the semiconductor layer with an impurity element by using the plurality of second conductive patterns as masks to form second impurity regions in the semiconductor layer, the second impurity regions being overlapped with the first conductive pattern.

14. The method for manufacturing the semiconductor device according to claim 13, wherein the width of the first conductive pattern is wider than the sum of the widths of the plurality of second conductive patterns.

15. The method for manufacturing the semiconductor device according to claim 13, wherein the resist pattern is formed by using a photomask or a reticle that has a diffraction grating pattern or a semi-transparent film.

16. The method for manufacturing the semiconductor device according to claim 13, wherein the first conductive pattern and the plurality of second conductive patterns serve as a gate electrode.

17. The method for manufacturing the semiconductor device according to claim 13, wherein the second impurity regions are LDD regions.

18. The method for manufacturing the semiconductor device according to claim 13, wherein the pair of first impurity regions are a source region and a drain region.

19. A method for manufacturing a semiconductor device comprising the steps of:

forming a first insulating film on a substrate;

forming a semiconductor layer on the first insulating film;

forming a second insulating film on a semiconductor layer;

forming a first conductive film on the insulating film;

forming a second conductive film on the first conductive film;

forming a resist pattern on the second conductive film having a concave upper surface;

etching the second conductive film and the first conductive film to form a first conductive pattern from the first conductive film and a plurality of second conductive patterns from the second conductive film, the plurality of second conductive patterns being located apart from each other on the first conductive pattern;

doping the semiconductor layer with an impurity element by using the first conductive pattern and the plurality of second conductive patterns as masks to form a pair of first impurity regions in the semiconductor layer, both of the first impurity regions being located outside the first conductive pattern;

doping the semiconductor layer with an impurity element by using the plurality of second conductive patterns as masks to form second impurity regions in the semiconductor layer, the second impurity regions being overlapped with the first conductive pattern;

forming a third insulating film over the first conductive pattern and the plurality of second conductive patterns;

forming a source electrode and a drain electrode over the third insulating film; and

forming a pixel electrode connected to one of the source electrode and the drain electrode.

20. The method for manufacturing the semiconductor device according to claim 19, wherein the width of the first conductive pattern is wider than the sum of the widths of the plurality of second conductive patterns.

21. The method for manufacturing the semiconductor device according to claim 19, wherein the resist pattern is formed by using a photomask or a reticle that has a diffraction grating pattern or a semi-transparent film.

22. The method for manufacturing the semiconductor device according to claim 19, wherein the first conductive pattern and the plurality of second conductive patterns serve as a gate electrode.

23. The method for manufacturing the semiconductor device according to claim 19, wherein the second impurity regions are LDD regions.

24. The method for manufacturing the semiconductor device according to claim 19, wherein the pair of first impurity regions are a source region and a drain region.