Semiconductor device and method of manufacture thereof

• US 7,579,241 B2
• Filed: 04/25/2007
• Issued: 08/25/2009
• Est. Priority Date: 02/24/2004
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hieda, Katsuhiko, Hagishima, Daisuke
• Primary Examiner(s): Booth; Richard A.
• Application Number:
  US11/790,391
• Publication Number:
  US 20070287245A1
• Time in Patent Office: 853 Days
• Field of Search: 438257-267, 257/E21.176
• US Class Current: 438/259
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming an island semiconductor portion comprising a first side surface and a second side surface opposed to the first side surface in a main surface of a semiconductor substrate or above the semiconductor substrate by forming a trench in the main surface of the semiconductor substrate;

forming a first insulating film on a top surface of the island semiconductor portion;

forming a second insulating film on the first and second side surfaces of the island semiconductor portion

forming a first conductive film on a region including the island semiconductor portion, the first insulating film, and the second insulating film;

forming a charge storage layer selectively on a side surface of the first insulating film and a side surface of the second insulating film by overall etching of the first conductive film such that the first conductive film remains on both the side surface of the first insulating film and the side surface of the second insulating film, the charge storage layer comprising a first sidewall provided on the first side surface of the island semiconductor portion and a second sidewall provided on the second side surface of the island semiconductor portion;

forming a third insulating film on the charge storage layer; and

forming a control gate electrode on the third insulating film.

2. The method according to claim 1, wherein the second insulating film is a tunnel insulating film.

3. The method according to claim 2, wherein the tunnel insulating film includes a laminated film including a silicon oxide film and silicon nitride film or an aluminum oxide film.

4. The method according to claim 1, wherein the third insulating film is a monolayer oxide film including Al, Ta, Ti, Sr, Hf, or Zr, a laminated film including at least two of the monolayer oxide film, a laminated film including the monolayer oxide film and a silicon oxide film, a laminated film including the monolayer oxide film and a silicon nitride film, a laminated film including the laminated film including the at least two of the monolayer oxide film and a silicon oxide film, or a laminated film including the laminated film including the at least two of the monolayer oxide film and a silicon nitride film.

5. The method according to claim 1, wherein the island semiconductor portion is surrounded by the trench.

6. The method according to claim 1, further comprising forming source/drain diffusion layers in the main surface.