Hermetic packaging and method of manufacture and use therefore

• US 7,579,663 B2
• Filed: 02/11/2008
• Issued: 08/25/2009
• Est. Priority Date: 08/07/2002
• Status: Expired due to Fees

• Current Assignee: Chang-Feng Wan
• Original Assignee: Chang-Feng Wan
• Inventors: Wan, Chang-Feng
• Primary Examiner(s): Cao; Phat X
• Application Number:
  US12/028,841
• Publication Number:
  US 20080308920A1
• Time in Patent Office: 561 Days
• Field of Search: 257/415, 257/419, 257/420, 438/50, 438/52, 438/53
• US Class Current: 257/415
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2203/0118 Cantilevers
• CPC Class Codes: B81B 2203/0307 Anchors
• CPC Class Codes: B81B 2203/0384 sloped profile
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00095 Interconnects
• CPC Class Codes: B81C 1/00285 using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: H01G 5/16 using variation of distance between electrodes
• CPC Class Codes: H01G 5/40 Structural combinations of variable capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01L 29/82 controllable by variation of the magnetic field applied to the device

Abstract

A system and method for manufacturing micro cavity packaging enclosure at the wafer level using MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed from epoxy-bonded single-crystalline silicon wafer as its cap, epoxy and deposited metal or insulator as at least part of its sidewall, on substrate wafers.

Claims

1. A plurality of vacuum or hermetic packaging enclosures formed on an IC wafer comprising

a sidewall formed from an adhesive layer and a deposited film;

a cap wafer formed from silicon or glass wafer;

a substrate or bottom wafer formed from said IC wafer;

wherein said adhesive layer is substantially flat and bonds a part of the bottom side of said cap wafer to a part of the top side of said substrate wafer, wherein said adhesive layer is a spacer creating a gap between said cap wafer and said substrate wafer, said adhesive layer is substantially removed from said enclosure and/or said sidewall to create cavity in said enclosure, said deposited film is a metal or a ceramic layer, wherein said deposited film directly adheres to the entire side surfaces of said enclosure, including the entire side surfaces of said cap wafer and said adhesive polymer layer, and at least a part of said top side surface of said substrate;

said adhesive layer extends beyond the outer rim of said cap wafer, and said metal or ceramic layer does not cover said IC wafer completely.

2. The enclosure of claim 1, wherein said adhesive layer is a photosensitive adhesive polymer.

3. The enclosure of claim 2, wherein said photosensitive adhesive polymer forms a ring pattern surrounding said cavity.

4. The enclosure of claim 1 further comprises etch access holes.

5. The etch access holes of claim 4 are sealed with deposited films.

6. The etch access holes of claim 4 are formed on said cap wafer.

7. The etch access hole of claim 4 are formed on said Cap wafer.

8. The etch access holes of claim 4 are formed on said sidewalls.