Low power comsumption, low noise and high power gain distributed amplifiers for communication systems

• US 7,579,913 B1
• Filed: 02/27/2008
• Issued: 08/25/2009
• Est. Priority Date: 02/27/2008
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Cheng, Yu, Chang, Jen-Chung, Yen, Albert Kuo-Huei
• Primary Examiner(s): CHOE, HENRY
• Application Number:
  US12/038,374
• Publication Number:
  US 20090212868A1
• Time in Patent Office: 545 Days
• Field of Search: 330/286, 330/295, 330/124.R, 330/54
• US Class Current: 330/286
• CPC Class Codes: H03F 2203/45212 the differential amplifier being designed to have a reduced offset
• CPC Class Codes: H03F 3/605 Distributed amplifiers

Abstract

Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respectively and for preventing signal reflection in the input transmission line and the output transmission line, respectively; multi-stage Gm cells with common mode feedback, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and an input gate bias circuit, for providing bias for the multi-stage Gm cells. In at least one of the Gm cells, one inverter performs V/I conversion while other inverters provide negative resistance to control common mode of output voltage and to enhance DC gain of the Gm cell. Due to common mode feedback, no output gate bias is needed.

Claims

1. A distributed amplifier in an RF signal transreceiver, the distributed amplifier comprising:

an input transmission line, having an input for receiving an input signal to be amplifier;

an output transmission line, having an output at which an output signal is provided;

an input impedance match, for providing termination of the input transmission line and for preventing signal reflection in the input transmission line;

an output impedance match, for providing termination of the output transmission line and for preventing signal reflection in the output transmission line;

multi-stage Gm (transconductance) cells with common mode feedback, coupled between the input transmission line and the output transmission line, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and

an input gate bias circuit, for providing bias for the multi-stage Gm cells;

wherein at least one of the Gm cells including a plurality of inverters, one of the inverters being for performing V/I conversion, and the others of the inverters being for providing negative resistance to control common mode of output voltages of the Gm cell and to enhance DC gain of the Gm cell.

2. The distributed amplifier as set forth in claim 1, when the input signal travels through the input transmission line, the Gm cells become excited by the input signal and transfers the input signal to the output transmission line through their transconductance.

3. The distributed amplifier as set forth in claim 1, when the signals output by the Gm cells are summed at the output of the output transmission line.

4. The distributed amplifier as set forth in claim 1, wherein the input transmission line includes:

first inductors at beginning and end of the input transmission line; and

a series of second inductors connected between the first inductors.

5. The distributed amplifier as set forth in claim 4, wherein the input impedance match includes:

a first resistance coupled to the first conductor at the end of the input transmission line; and

a first RF bypass capacitor coupled between the first resistance and GND.

6. The distributed amplifier as set forth in claim 1, wherein the output transmission line includes:

third inductors at beginning and end of the output transmission line; and

a series of fourth inductors connected between the third inductors.

7. The distributed amplifier as set forth in claim 6, wherein the output impedance match includes:

a second resistance coupled to the third conductor at the end of the output transmission line; and

a second RF bypass capacitor coupled between the second resistance and GND.

8. The distributed amplifier as set forth in claim 1, wherein the input gate bias circuit includes:

a current source; and

a first transistor, the drain of the first transistor coupled to both its gates and the current source, the gate of the first transistor indirectly coupled to the input transmission line;

wherein equal bias currents are established in each of the Gm cells and the bias currents are substantially equal to the current supplied by the current source.

9. The distributed amplifier as set forth in claim 1, wherein, for the at least one of the Gm cells, the others of the inverters being for providing negative resistance include at least four parallel and serially connected inverters, the negative resistance being implemented by choosing:

gm4>

gm5, gm3=gm4, gm2=gm5,

gm2˜

gm5 refer to transconductance values of the four parallel and serially connected inverters.

10. The distributed amplifier as set forth in claim 9, wherein, for the at least one of the Gm cells, two of the four parallel and serially connected inverters are shunted as resistors connected between an output node of the Gm cell and a common mode voltage level.

11. The distributed amplifier as set forth in claim 10, wherein, for the at least one of the Gm cells, the other two of the four parallel and serially connected inverters inject currents to the two of the four parallel and serially connected inverters, respectively.

12. A distributed amplifier in an RF signal transreceiver, the distributed amplifier comprising:

an input transmission line, having an input for receiving an input signal to be amplifier;

an output transmission line, having an output at which an output signal is provided;

an input impedance match, for providing termination of the input transmission line and for preventing signal reflection in the input transmission line;

an output impedance match, for providing termination of the output transmission line and for preventing signal reflection in the output transmission line;

multi-stage Gm (transconductance) cells with common mode feedback, coupled between the input transmission line and the output transmission line, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and

an input gate bias circuit, for providing bias for the multi-stage Gm cells;

wherein at least one of the Gm cells including;

a first CMOS inverter, coupled between an input node and an output node of the Gm cell, the first CMOS inverter being for performing V/I conversion; and

second, third, fourth and fifth CMOS inverters, coupled to the first CMOS inverter, the second, third, fourth and fifth CMOS inverters being for providing negative resistance to control common mode of output voltages of the Gm cell and to enhance DC gain of the Gm cell;

the negative resistance, expressed by expressed by

$\mathrm{gn}=-\frac{1}{\mathrm{gm}<br><br><br><br>4-\mathrm{gm}<br><br><br><br>5},$

being implemented by choosing;

gm4>

gm5, gm3=gm4, gm2=gm5,

gm2˜

gm5 refer to transconductance values of the second, third, fourth and fifth CMOS inverters.

13. The distributed amplifier as set forth in claim 12, when the input signal travels through the input transmission line, the Gm cells become excited by the input signal and transfers the input signal to the output transmission line through their transconductance.

14. The distributed amplifier as set forth in claim 12, when the signals output by the Gm cells are summed at the output of the output transmission line.

15. The distributed amplifier as set forth in claim 12, wherein the input transmission line includes:

first inductors at beginning and end of the input transmission line; and

a series of second inductors connected between the first inductors.

16. The distributed amplifier as set forth in claim 15, wherein the input impedance match includes:

a first resistance coupled to the first conductor at the end of the input transmission line; and

a first RF bypass capacitor coupled between the first resistance and GND.

17. The distributed amplifier as set forth in claim 12, wherein the output transmission line includes:

third inductors at beginning and end of the output transmission line; and

a series of fourth inductors connected between the third inductors.

18. The distributed amplifier as set forth in claim 17, wherein the output impedance match includes:

a second resistance coupled to the third conductor at the end of the output transmission line; and

a second RF bypass capacitor coupled between the second resistance and GND.

19. The distributed amplifier as set forth in claim 12, wherein the input gate bias circuit includes:

a current source; and

a first transistor, the drain of the first transistor coupled to both its gates and the current source, the gate of the first transistor indirectly coupled to the input transmission line;

wherein equal bias currents are established in each of the Gm cells and the bias currents are substantially equal to the current supplied by the current source.

20. The distributed amplifier as set forth in claim 12, wherein, for the at least one of the Gm cells,

the third and the fourth CMOS inverters are shunted as resistors connected between an output node of the Gm cell and a common mode voltage level;

and

the second and the fifth CMOS inverters inject currents to the third and the fourth inverters, respectively.