Communications systems and methods

• US 7,580,380 B2
• Filed: 05/21/2004
• Issued: 08/25/2009
• Est. Priority Date: 05/28/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Artimi Ltd. (Veebeam Corporation)
• Inventors: Baker, David, Moore, Mark Justin
• Primary Examiner(s): Jung, Min
• Application Number:
  US10/516,747
• Publication Number:
  US 20060120433A1
• Time in Patent Office: 1,922 Days
• Field of Search: 370/310, 370/315, 370/338, 370/351, 370/389, 370/400
• US Class Current: 370/310
• CPC Class Codes: H04B 1/7163 using impulse radio
• CPC Class Codes: H04W 84/18 Self-organising networks, e.g. ad-hoc networks or sensor networks

Abstract

This invention generally relates to networks of communications devices, in particular ultra wideband (UWB) communications devices. An ultra-wideband (UWB) network comprising a plurality of UWB devices each forming a node of said network, pairs of said UWB devices being configured for communication with one another using one of a plurality of UWB channels, each said UWB device comprising a UWB transceiver for bidirectional communication over one or more of said UWB channels with at least one other of said UWB devices; and a device controller coupled to said UWB transceiver, said controller being configured to determine a said UWB channel for use in establishing a communication link with each other UWB device; whereby said network is configured for automatic construction of a set of communications links between said nodes of said network.

Claims

1. A controller for an ultra-wideband (UWB) network node, the controller comprising:

a processor having a processor control bus and a processor data bus;

processor memory coupled to said processor data bus;

buffer memory coupled to a second data bus;

a memory access controller coupled to said second data bus and to said processor control bus; and

a UWB interface for interfacing to a UWB communications device, coupled to said processor control bus and to said second data bus; and

wherein said processor is master of said processor control bus and said memory access controller is master of said second data bus.

2. The controller of claim 1, wherein the processor memory includes program memory and/or data memory.

3. The controller of claim 2, wherein the memory access controller is configured to move packet header data from the buffer memory to the data memory.

4. The controller of claim 1 further comprising a second interface coupled to said processor control bus and to said second data bus.

5. The controller of claim 4, wherein the second interface includes at least one of:

a PCI interface, an Ethernet interface, or a second UWB interface.

6. The controller of claim 4, wherein the second interface interfaces to a host processor associated with at least one of:

a television, a computer, or a set top box.

7. The controller of claim 1, wherein the UWB communications device performs forward error correction.

8. The controller of claim 1, wherein the buffer memory is used to buffer transmitted packet data.

9. The controller of claim 1, wherein the memory access controller includes a plurality of registers accessible to the processor via the processor control bus.

10. The controller of claim 9, wherein the plurality of registers is used to store packet control information.

11. The controller of claim 10, wherein the packet control information includes channel handle information.

12. The controller of claim 1, further comprising additional memory appended to the buffer memory.

13. The controller of claim 1, wherein the additional memory includes at least one of:

flash memory or SDRAM.