Method and apparatus for channel amplitude estimation and interference vector construction

• US 7,580,448 B2
• Filed: 10/15/2003
• Issued: 08/25/2009
• Est. Priority Date: 10/15/2002
• Status: Active Grant

• Current Assignee: III Holdings 1, LLC (Intellectual Ventures LLC)
• Original Assignee: TensorComm, Inc. (Rambus Inc.)
• Inventors: Narayan, Anand P., Jain, Prashant
• Primary Examiner(s): Ahn, Sam K
• Application Number:
  US10/686,829
• Publication Number:
  US 20040098433A1
• Time in Patent Office: 2,141 Days
• Field of Search: 375/142, 375/143, 375/144, 375/148, 375/150, 375/152, 375/316, 375/343, 375/346, 375/349, 455/63.1, 455/114.2, 455/278.1, 455/296, 455/278, 708/410
• US Class Current: 375/148
• CPC Class Codes: H04B 1/7107 Subtractive interference cancellation
• CPC Class Codes: H04B 1/7117 Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
• CPC Class Codes: H04B 2001/70935 using a bank of matched fileters, e.g. Fast Hadamard Transform
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates
• CPC Class Codes: H04B 2201/70707 Efficiency-related aspects
• CPC Class Codes: H04J 11/0056 Inter-base station aspects
• CPC Class Codes: H04J 13/0048 Walsh

Abstract

The present invention is directed to an efficient method and apparatus for channel determination and interference vector construction in accordance with spread spectrum systems. Channel determination is performed using a first series of fast Walsh transform steps. The results of the first set of fast Walsh transform steps corresponding to valid communication system channels are compared to a threshold value. Results derived from the first set of fast Walsh transform steps are then passed through a second set of fast Walsh transform steps with the number of steps performed for a set of results determined by the symbol length associated with the channels from which the amplitude information was derived. The interference vectors thus obtained for each valid symbol length may then be combined to form a composite interference vector. The fast Walsh transform steps and other steps may be performed using shared hardware components or software modules.

Claims

1. A method for signal processing comprising:

performing a first fast Walsh transform on a first set of magnitudes to obtain a result;

modifying the said result to obtain a first modified result;

performing at least a second fast Walsh transform on the said first modified result to obtain a second modified result;

where modifying the said result comprises;

storing a result of said performing a first fast Walsh transform in a first register;

comparing each magnitude comprising said result of performing said at least a first fast Walsh transform to a threshold value; and

replacing each magnitude of said stored result of performing said first fast Walsh transform that is greater than said threshold value with a zero to obtain the first modified result.

2. An apparatus for interference cancellation, comprising:

means for receiving a signal;

means for despreading the received signal;

means for performing carrier phase recovery on the despread signal;

means for performing at least a first fast Walsh transform on the despread carrier phase recovered signal to obtain a first set of transformed values;

means for modifying the said first set of transformed values to create a first modified set of values; and

means for performing at least a second fast Walsh transform on said first modified set of values to create a second modified set of values, further comprising;

means for storing an interference vector precursor, wherein said interference vector precursor includes an element amplitude for an element having an amplitude that exceeds a threshold and a zero for an element having an amplitude that does not exceed said threshold.

3. The apparatus of claim 2, further comprising:

means for performing at least a first fast Walsh transform on said interference vector precursor to obtain an interference vector.

4. The apparatus of claim 3, further comprising:

means for storing said interference vector.

5. The apparatus of claim 3, further comprising:

means for scaling said interference vector.

6. The apparatus of claim 5, further comprising means for combining a plurality of interference vectors to form a composite interference vector.

7. A receiver device, comprising:

a despreader operable to despread a received signal to produce a despread signal;

a carrier phase recovery module coupled to the despreader;

a fast Walsh transform module operable to perform a selected fast Walsh transform stage on the output of the carrier phase recovery module;

a comparator operable to compare each value output from said fast Walsh transform module to a threshold;

a first memory register operable to store element values output from said comparator as having a value less than said threshold; and

a second memory register operable to store element values output from said comparator as having a value not less than said threshold.

8. The device of claim 7, wherein said comparator is additionally operable to output a zero for storing in said first memory register in place of element values having a value greater than said threshold.

9. The device of claim 7, wherein said comparator is additionally operable to output a zero for storing in said second memory register in place of element values having a value less than said threshold.

10. The device of claim 7, further comprising:

a multiplexer operable to provide said element values stored in said second memory to said fast Walsh transform module, said fast Walsh transform module additionally being operable to perform at least a first fast Walsh transform on said stored element values to obtain an interference vector.

11. The device of claim 10, further comprising:

a scaler operable to multiply said interference vector by a selected value.

12. The device of claim 11, further comprising a summer operable to add a plurality of scaled interference vectors to obtain a composite interference vector.

13. A method implemented in a logic circuit configured for:

performing carrier phase recovery on and despreading a received signal to obtain a first set of magnitudes;

performing at least a first fast Walsh transform on said first set of magnitudes, wherein said set of magnitudes contains a number of magnitudes that is equal to a number of chips in a longest valid symbol;

storing a result of said performing at least a first fast Walsh transform in a first register;

comparing each magnitude comprising said result of performing said at least a first fast Walsh transform to a threshold value; and

storing each magnitude of said stored result of performing said first fast Walsh transform that is greater than said threshold value to obtain a first modified result, further configured for;

storing each magnitude comprising said result of performing an n^th fast Walsh transform having a magnitude that is not less than said threshold value in a second register; and

storing a zero for magnitudes comprising said result of performing said n^th fast Walsh transform having a magnitude that is less than said threshold value in said second register, wherein said second register comprises a number of magnitudes that is equal to said number of chips in a longest valid symbol, and wherein n is a number of fast Walsh transforms performed.

14. The method of claim 13, wherein said storing a zero comprises replacing magnitudes stored in said second register having a magnitude that is not greater than said threshold value with a zero.

15. The method of claim 13, wherein said n^th fast Walsh transform corresponds to a Walsh code set for symbols of a valid length.

16. The method of claim 13, further configured for:

storing said magnitude comprising said result of performing an (n−

1)^th fast Walsh transform having a magnitude that is greater than said threshold value in a third register; and

storing a zero for magnitudes comprising said result of performing said (n−

1)^th fast Walsh transform having a magnitude that is not greater than said threshold value in said third register, wherein said third register comprises a number of magnitudes that is equal to said number of chips in a longest valid symbol.

17. The method of claim 16, wherein said (n−

1)^th fast Walsh transform corresponds to a Walsh code set for symbols of at least a minimum valid length.

18. The method of claim 13, wherein said second register comprises a number of values equal to said number of chips in a longest valid symbol.

19. The method of claim 16, further configured for:

adding said value in said second register to a product equal to said value in said third register multiplied by 2 to obtain a composite interference vector.

20. The method of claim 19, wherein said n^th fast Walsh transform corresponds to a Walsh code set for symbols of a maximum valid length.

21. The method of claim 19, further configured for:

applying said composite interference vector to a received signal stream to create an interference canceled signal stream.