Generation and detection of non-binary digital sequences

• US 7,580,472 B2
• Filed: 02/25/2005
• Issued: 08/25/2009
• Est. Priority Date: 02/25/2004
• Status: Expired due to Fees

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): TAYONG, HELENE E
• Application Number:
  US11/065,836
• Publication Number:
  US 20050184888A1
• Time in Patent Office: 1,642 Days
• Field of Search: 375/286, 364/717, 380/46, 331/78, 341/57, 708/492
• US Class Current: 375/286
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04J 13/10 Code generation

Abstract

Method and apparatus for generating ternary and multi-valued Gold sequences, are disclosed. Also methods to detect ternary and multi-valued sequences are disclosed. The detection can be performed by a ternary or multi-valued LFSR descrambler when the sequences are generated by an LFSR based sequence generator. A wireless system which can assign additional sequences to designated users is also disclosed. The wireless system can also transfer information to user equipment that enables methods for sequence generation and sequence detection.

Claims

1. An apparatus for generating a set of sequences of ternary signals wherein each multi-value signal can assume one of three states, comprising:

a first sequence generator that can generate a first sequence of ternary signals wherein each multi-value signal can assume one of 3 states on an output of the first sequence generator;

a second sequence generator that can generate a set of 3^p−

1 with p>

1 different but related second sequences of ternary signals wherein each multi-value signal can assume one of 3 states on an output of the second sequence generator wherein each different sequence is formed by phase shifting each element of the previous sequence by one position in a circular fashion;

a first ternary logic device having a first input connected to the output of the first sequence generator and a second input connected to the output of the second sequence generator;

wherein a set of 3^p−

1 different ternary Gold sequences is generated on an output of the first ternary logic device, the set of ternary Gold sequences characterized by;

an auto-correlation with a single peak value on the coinciding phase of the correlation between the generated ternary sequence and a phase shifted copy of itself and a correlation value that is limited to a lower maximum and minimum value in all other phases;

a cross-correlation value between each of the generated sequences that is limited to a maximum and minimum value that is lower than the peak value of the auto-correlation of each individual sequence; and

a correlation value between two ternary signals being determined by including a step of adding a first value to a sum whenever the two ternary signals are determined to be equal.

2. A method for generating on an output of a sequence generator a sequences of multi-valued signals, a multi-valued signal able to assume one of x states, x being greater than or equal to three, comprising:

generating with a first device a first sequence of multi-valued signals wherein each multi-valued signal can assume one of x states;

generating with a second device a second sequence of multi-valued signals wherein each multi-valued signal can assume one of x states;

inputting the first sequence of multi-valued signals and the second sequence of multi-valued signals on the sequence generator having at least a first multi-valued logic device having at least two inputs and an output, the first multi-valued logic device implementing an x-valued logic function and generating a third sequence of multi-valued signals on the output of the sequence generator wherein each multi-valued signal can assume one of x states; and

determining by a correlating device a correlation value for the third sequence of multi-valued signals by including a step of adding a first value to a sum whenever a multi-valued signal in the third sequence is determined to be identical to a corresponding signal in a fourth sequence of signals.

3. The method as claimed in claim 2, wherein the step of generating the first sequence of multi-valued signals is performed using a first multi-element shift register.

4. The method as claimed in claim 3, wherein the step of generating the second sequence of multi-valued signals is performed using a second multi-element shift register.

5. The method as claimed in claim 2, wherein the step of generating the first sequence of multi-valued signals is performed using a first multi-element shift register and at least a second multi-valued logic device that implements a second multi-valued logic function.

6. The method as claimed in claim 5, wherein the step of generating the second sequence of multi-valued signals is performed using a second multi-element shift register and at least a third multi-valued logic device that implements a third multi-valued logic function.

7. The method as claimed in claim 6, wherein the third sequence of multi-valued signals is a Gold sequence.

8. An apparatus for generating a sequences of multi-value signals wherein each multi-value signal can assume one of x states, x being greater than or equal to three, comprising:

a first sequence generator that can generate a first sequence of multi-value signals wherein each multi-value signal can assume one of x states on an output of the first sequence generator;

a second sequence generator that can generate a second sequence of multi-value signals wherein each multi-value signal can assume one of x states on an output of the second sequence generator; and

a third sequence generator having at least a first and a second input and an output, wherein;

the first input is enabled to receive the first sequence of multi-value signals;

the second input is enabled to receive the second sequence of multi-value signals;

the output is enabled to generate the sequence of multi-value signals; and

at least one of the first, the second and the third sequence generator implements a reversible non-commutative x-valued logic function.

9. The apparatus as claimed in claim 8, wherein the first sequence generator includes a first multi-element shift register.

10. The apparatus as claimed in claim 9, wherein the second sequence generator includes a second multi-element shift register.

11. The apparatus as claimed in claim 8, wherein the first sequence generator includes a first multi-element shift register and at least a second multi-value logic device that implements a second multi-value logic function.

12. The apparatus as claimed in claim 11, wherein the second sequence generator includes a second multi-element shift register and at least a third multi-value logic device that implements a third multi-value logic function.

13. The apparatus as claimed in claim 12, wherein the third sequence of multi-value signals is a Gold sequence.

14. The apparatus as claimed in claim 8, wherein the apparatus is included in a communication system.

15. A method for generating a sequence of multi-value signals, wherein a multi-value signal can assume one of x states, x being greater than or equal to three, comprising:

generating by a first sequence generator a first sequence of multi-value signals wherein a multi-value signal can assume one of x states;

generating by a second sequence generator a second sequence of multi-value signals wherein a multi-value signal can assume one of x states;

inputting the first sequence of multi-value signals and the second sequence of multi-value signals on a third sequence generator having at least a first and a second input and an output, wherein at least one of the first, the second and the third sequence generator implements at least one of the group consisting of a non-commutative x-valued logic function and a x-valued inverter not inverting state 0 to state 0; and

generating the sequence of multi-value signals on the output of the third sequence generator.

16. The method as claimed in claim 15, wherein the step of generating the first sequence of multi-value signals is performed using a first multi-element shift register.

17. The method as claimed in claim 16, wherein the step of generating the second sequence of multi-value signals is performed using a second multi-element shift register.

18. The method as claimed in claim 15, wherein the step of generating the first sequence of multi-value signals is performed using a first multi-element shift register and at least a second multi-value logic device that implements a second multi-value logic function.

19. The method as claimed in claim 18, wherein the step of generating the second sequence of multi-value signals is performed using a second multi-element shift register and at least a third multi-value logic device that implements a third multi-value logic function.

20. The method as claimed in claim 19, wherein the third sequence of multi-value signals is a Gold sequence.

21. A detector for detecting a sequence of n-valued symbols with n>

2 generated by a sequence generator, comprising;

an n-valued Linear Feedback Shift Register (LFSR), the n-valued LFSR including;

a shift register of k with k>

1 n-valued elements, the shift register having an input, the input enabled to receive the sequence of n-valued symbols;

an implementation of an n-valued function, including a first and a second input and an output; and

an implementation of an n-valued detecting function with a first and a second input and an output, the first input enabled to receive the sequence of n-valued symbols and being connected to the input of the shift register, the second input being connected to the output of the implementation of the n-valued function and the output of the implementation of the n-valued detecting function enabled to provide a sequence of symbols indicating detection of the sequence of n-valued symbols.

22. The detector as claimed in claim 21, wherein the output of the implementation of the n-valued detecting function provides a symbol in a first state when symbols received on the first and second input of the implementation of the n-valued detecting function have the same state and wherein the output of the implementation of the n-valued detecting function provides a symbol not in a first state when symbols received on the first and second input of the implementation are different in state.

23. The detector as claimed in claim 22, wherein at most k symbols in the sequence of symbols indicating detection are not in a first state when the sequence of n-valued symbols is being detected.

24. The detector as claimed in claim 21, wherein the detector is included in a communication system.