Method of design analysis of existing integrated circuits

• US 7,580,557 B2
• Filed: 08/29/2008
• Issued: 08/25/2009
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: TechInsights, Inc. (M3, Inc.)
• Original Assignee: Semiconductor Insights Incorporated (Informa PLC)
• Inventors: Begg, Stephen, Gont, Val, Zavadsky, Vyacheslav L., Abt, Jason, Keyes, Edward
• Primary Examiner(s): Bella; Matthew C
• Assistant Examiner(s): RAHMJOO, MANUCHEHR
• Application Number:
  US12/200,968
• Publication Number:
  US 20080317327A1
• Time in Patent Office: 361 Days
• Field of Search: 382/141, 382/144, 382/145, 382/147, 382/148
• US Class Current: 382/141
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: G06T 7/74 involving reference images or patches

Abstract

The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Claims

1. A rigid comparison method of determining whether a possible location of a standard cell in an image of an IC layout is a true high probability match of the standard cell represented by a template comprising:

computing gradients for the template and a possible location from a set of possible locations;

computing a first set of dot products of the gradients;

applying morphological dilation of the first set of dot products to obtain a second set of dot products;

determining order statistics on the second set of dot products; and

determining if the order statistics are below a predefined threshold,

wherein if the order statistics are less than said predefined threshold, the possible location is a true instance of the standard cell.

2. Apparatus for determining whether a possible location of a standard cell in an image of an IC layout is a high probability match of the standard cell represented by a template using a rigid comparison method comprising:

means for computing gradients for the template and a possible location from a set of possible locations;

means for computing a first set of dot products of the gradients;

means for applying morphological dilation of the first set of dot products to obtain a second set of dot products;

means for determining order statistics on the second set of dot products; and

means for determining if the order statistics are below a predefined threshold,

wherein if the order statistics are less than said predefined threshold, the possible location is a high probability match of the standard cell.