Procedure and device for programming a DMA controller in which a translated physical address is stored in a buffer register of the address processing unit and then applied to the data bus and stored in a register of the DMA controller

• US 7,581,039 B2
• Filed: 07/11/2005
• Issued: 08/25/2009
• Est. Priority Date: 07/12/2004
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Martinez, Albert, Nicolai, Jean
• Primary Examiner(s): Tsai; Henry W. H.
• Assistant Examiner(s): RHU, KRIS M
• Application Number:
  US11/179,033
• Publication Number:
  US 20060020719A1
• Time in Patent Office: 1,506 Days
• Field of Search: 710/26
• US Class Current: 710/22
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the virtual address is translated into a corresponding physical address, and the physical address is stored in a buffer register that is inaccessible to the user program. In response to a second instruction of the user program, the physical address stored in the buffer register is applied to the data bus and a first word including high-order bits indicating the base subaddress is applied to the address bus. The source or destination register is selected according to the first word applied to the address bus and the physical address applied to the data bus is stored in the selected register.

Claims

1. A method for a user program running in user mode to directly program a DMA controller of a system on a chip, the system on a chip including a central processing unit, a memory management unit for translating virtual addresses according to a translation table, an address bus, a data bus, an address processing unit coupled between the central processing unit and the address and data buses, and the DMA controller, the DMA controller including at least one set of registers having a base subaddress that is used to address registers of the set of registers, the registers of the set of registers including a source register, a destination register, and a size register, said method comprising the steps of:

in response to a first dedicated instruction of the user program that includes an address argument indicating a virtual address corresponding to the physical address to be stored in the source or destination register of the DMA controller, translating the virtual address into the corresponding physical address and storing the corresponding physical address in a buffer register of the address processing unit that cannot be accessed by the user program; and

in response to a second dedicated instruction of the user program that includes an address argument indicating the virtual address corresponding to the physical address to be stored in the source or destination register of the DMA controller;

applying the corresponding physical address stored in the buffer register of the address processing unit to the data bus and a first word that includes at least high-order bits indicating the base subaddress of the set of registers to the address bus; and

in response to the first word being applied to the address bus, selecting the source or destination register of the DMA controller and storing the corresponding physical address applied to the data bus in the selected register of the DMA controller,

wherein the first dedicated instruction and the second dedicated instruction are instructions dedicated to directly programming the DMA controller, and

the second dedicated instruction is different than and after the first dedicated instruction.

2. The method according to claim 1, wherein each of the registers of the set of registers of the DMA controller has a physical address encoded on a number N of bits made up of the high-order bits indicating the base subaddress of the set of registers followed by bits defining an offset in the set.

3. The method according to claim 1,

wherein the first dedicated instruction also includes a data argument indicating a size, and the method further comprises the steps of:

in response to the first dedicated instruction, applying the data argument to the data bus and a second word including the high-order bits indicating the base subaddress of the set of registers to the address bus; and

selecting the size register as a function of the second word applied to the address bus in response to the first dedicated instruction, and storing the data argument applied to the data bus in the size register.

4. The method according to claim 1,

wherein the set of registers of the DMA controller also includes at least one status register, and

the method further comprises the steps of:

in response to a third dedicated instruction of the user program, applying at least a third word including the high-order bits indicating the base subaddress of the set of registers to the address bus; and

selecting the status register in response to the third word being applied to the address bus, and applying content of the status register to the data bus.

5. The method according to claim 4, further comprising the steps of:

in response to the first dedicated instruction, determining a first identifier of the user program and storing the first identifier in an identifier register of the address processing unit;

in response to at least one of the second and third dedicated instructions, determining a second identifier of the user program, and comparing the second identifier to the first identifier stored in the identifier register of the address processing unit;

if the determination was in response to the second dedicated instruction, applying the physical address stored in the buffer register of the address processing unit to the data bus and the first word to the address bus only if the first and second identifiers match; and

if the determination was in response to the third dedicated instruction, applying the third word to the address bus only if the first and second identifiers match.

6. The method according to claim 5, wherein each of the identifiers of the user program is an address space identifier which is stored in the translation table of the memory management unit for each user program of the system on a chip, and which is delivered by the memory management unit when translating a virtual address that is supplied as an address argument of an instruction.

7. The method according to claim 5,

wherein at least one word from the first word and the third word applied to the address bus also includes the first or second identifier of the user program, and

one of the registers of the DMA controller is selected as a function of the first or second identifier in the one word that is applied to the address bus.

8. The method according to claim 1, wherein the DMA controller further includes a state machine for, when the first word is applied to the address bus, selecting the source or destination register of the DMA controller as a function of a current state of the state machine in an ordered cycle.

23. The method according to claim 1,

wherein the memory management unit includes a translation look-aside buffer comprising the translation table, and

the buffer register of the address processing unit in which the corresponding physical address is stored is different than the translation look-aside buffer of the memory management unit.

9. A system on a chip comprising:

an address bus;

a data bus;

a DMA controller coupled to the address bus and the data bus, the DMA controller including at least one set of registers having a base subaddress that is used to address registers of the set of registers, the registers of the set of registers including a source register, a destination register, and a size register;

an address processing block comprising;

a memory management unit including a translation look-aside buffer comprising a translation table, the memory management unit translating a virtual address into a corresponding physical address according to the translation table;

a set register for storing at least the base subaddress of the set of registers; and

a buffer register that is inaccessible to the user program, the buffer register being different than the translation look-aside buffer of the memory management unit; and

a central processing unit, the address processing block being coupled between the central processing unit and the address and data buses, the central processing unit executing a user program in user mode, the user program including first and second dedicated instructions that are instructions dedicated to directly programming the DMA controller,

wherein in response to the first dedicated instruction of the user program that includes an address argument indicating a virtual address corresponding to the physical address to be stored in the source or destination register of the DMA controller, the central processing unit supplies the virtual address indicated by the address argument of the first dedicated instruction to the memory management unit, the memory management unit translates the received virtual address into the corresponding physical address according to the translation table, and the buffer register of the address processing block stores the corresponding physical address resulting from the translation by the memory management unit,

in response to the second dedicated instruction of the user program that includes an address argument indicating the virtual address corresponding to the physical address to be stored in the source or destination register of the DMA controller;

the address processing block applies a first word that includes at least high-order bits indicating the base subaddress of the set of registers that is stored in the set register to the address bus, and applies to the data bus the corresponding physical address stored in the buffer register of the address processing block, and

in response to the first word being applied to the address bus, the DMA controller selects the source or destination register and stores the corresponding physical address applied to the data bus in the selected register, and

the second dedicated instruction is different than and after the first dedicated instruction.

10. The system on a chip according to claim 9, wherein each of the registers of the set of registers of the DMA controller has a physical address encoded on a number N of bits made up of the high-order bits indicating the base subaddress of the set of registers followed by bits defining an offset in the set.

11. The system on a chip according to claim 9,

wherein the first dedicated instruction also includes a data argument indicating a size,

in response to the first dedicated instruction, the address processing block applies to the data bus the data argument and to the address bus a second word including the high-order bits indicating the base subaddress of the set of registers that is stored in the set register, and

the DMA controller selects the size register as a function of the second word applied to the address bus and stores in the size register the data argument applied to the data bus.

12. The system on a chip according to claim 9,

wherein in response to a third dedicated instruction dedicated to DMA controller programming received by the central processing unit, the address processing block applies to the address bus a third word including the high-order bits indicating the base subaddress of the set of registers,

the set of registers of the DMA controller also includes a status register, and

the DMA controller, in response to the third word being applied to the address bus, selects the status register and applies content of the status register to the data bus.

13. The system on a chip according to claim 12,

wherein the address processing block determines, from the first dedicated instruction, a first identifier of the user program from which the first dedicated instruction originates, and determines, from at least one of the second and third dedicated instructions, a second identifier of the user program from which the second or third dedicated instruction originates,

the address processing block compares the first and second identifiers,

in response to the second dedicated instruction, the address processing block applies the physical address stored in the buffer register to the data bus and the first word to the address bus, only if the first and second identifiers match, and

in response to the third dedicated instruction, the address processing block applies the third word to the address bus only if the first and second identifiers match.

14. The system on a chip according to claim 13, wherein each of the identifiers of the user program is an address space identifier stored in the translation table of the memory management unit for each user program of the system on a chip, and is delivered during a translation operation of the memory management unit.

15. The system on a chip according to claim 13,

wherein each word applied by the address processing block to the address bus also includes the identifier that is determined from the instruction, and

the DMA controller selects a register as a function of the identifier in the word that is applied to the address bus.

16. The system on a chip according to claim 9, wherein the DMA controller further includes a state machine for, when the first word is applied to the address bus, selecting the source or destination register of the DMA controller as a function of a current state of the state machine in an ordered cycle.

17. An electronic device comprising at least one system on a chip according to claim 9.

18. A system on a chip comprising:

a central processing unit executing a user program in user mode, the user program including first and second dedicated instructions that are instructions dedicated to directly programming the DMA controller;

a DMA controller that includes at least one set of registers having a base subaddress that is used to address registers of the set of registers, the registers of the set of registers including a source register, a destination register, and a size register;

an address bus coupled to the DMA controller;

a data bus coupled to the DMA controller;

an address processing unit coupled between the central processing unit and the address and data buses;

first means for, in response to the first dedicated instruction of the user program that includes an address argument indicating a virtual address corresponding to the physical address to be stored in the source or destination register of the DMA controller, translating the virtual address into the corresponding physical address according to a translation table, and storing the corresponding physical address in a buffer register of the address processing unit that cannot be accessed by the user program; and

second means for, in response to the second dedicated instruction of the user program that includes an address argument indicating the virtual address corresponding to the physical address to be stored in the source or destination register of the DMA controller, applying the corresponding physical address stored in the buffer register of the address processing unit to the data bus and a first word that includes at least high-order bits indicating the base subaddress of the set of registers to the address bus,

wherein in response to the first word being applied to the address bus, the DMA controller selects the source or destination register of the DMA controller and stores the corresponding physical address applied to the data bus in the selected register, and

the second dedicated instruction is different than and after the first dedicated instruction.

19. The system on a chip according to claim 18, wherein each of the registers of the set of registers of the DMA controller has a physical address encoded on a number N of bits made up of the high-order bits indicating the base subaddress of the set of registers followed by bits defining an offset in the set.

20. The system on a chip according to claim 18,

wherein the first dedicated instruction also includes a data argument indicating a size,

the system on a chip further comprises fourth means for, in response to the first dedicated instruction, applying the data argument to the data bus and a second word including the high-order bits indicating the base subaddress of the set of registers to the address bus, and

the DMA controller selects the size register as a function of the second word applied to the address bus in response to the first dedicated instruction, and stores the data argument applied to the data bus in the size register.

21. The system on a chip according to claim 18,

wherein the set of registers of the DMA controller also includes at least one status register,

the system on a chip further comprises fourth means for, in response to a third dedicated instruction of the user program, applying a third word including the high-order bits indicating the base subaddress of the set of registers to the address bus, and

the DMA controller selects the status register in response to the third word being applied to the address bus, and applies content of the status register to the data bus.

22. The system on a chip according to claim 18, wherein the DMA controller further includes a state machine for, when the first word is applied to the address bus, selecting the source or destination register of the DMA controller as a function of a current state of the state machine in an ordered cycle.