Multiple processor system and method including multiple memory hub modules
First Claim
1. A memory system, comprising:
- a plurality of memory requestors;
a first rank containing a plurality of memory modules each of which comprises;
a plurality of memory devices; and
a memory hub coupled to a plurality of the memory requestors and to the memory devices in the memory module, the memory hub in each of the memory modules in the first rank including a plurality of first ports and being configured to allow any of the memory requesters to access the memory devices to which it is coupled or to access any of the first ports in the memory hub; and
a second rank containing a plurality of memory modules each of which comprises;
a plurality of memory devices; and
a memory hub coupled to the memory devices in the memory module, each of the memory modules in the second rank including a plurality of second ports corresponding in number to the number of memory modules in the first rank, the memory hub in each of the memory modules in the second rank being coupled to each of the memory modules in the first rank through respective ones of the first ports and the second ports, the memory hub in each of the memory modules in the second rank being operable to allow any of the memory requestors to access the memory devices to which it is coupled through at least one memory module in the first rank.
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Abstract
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.
284 Citations
11 Claims
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1. A memory system, comprising:
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a plurality of memory requestors; a first rank containing a plurality of memory modules each of which comprises; a plurality of memory devices; and a memory hub coupled to a plurality of the memory requestors and to the memory devices in the memory module, the memory hub in each of the memory modules in the first rank including a plurality of first ports and being configured to allow any of the memory requesters to access the memory devices to which it is coupled or to access any of the first ports in the memory hub; and a second rank containing a plurality of memory modules each of which comprises; a plurality of memory devices; and a memory hub coupled to the memory devices in the memory module, each of the memory modules in the second rank including a plurality of second ports corresponding in number to the number of memory modules in the first rank, the memory hub in each of the memory modules in the second rank being coupled to each of the memory modules in the first rank through respective ones of the first ports and the second ports, the memory hub in each of the memory modules in the second rank being operable to allow any of the memory requestors to access the memory devices to which it is coupled through at least one memory module in the first rank. - View Dependent Claims (2)
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3. A memory system, comprising:
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a plurality of memory requestors; and a first rank of memory modules each of which comprise; a plurality of memory devices; and a memory hub comprising; a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices in the memory module; a cross bar switch having a plurality of first switch ports, a plurality of second switch ports, and a plurality of memory ports, each of the first switch ports being coupled to a respective one of the memory requesters, and each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the memory requesters to any one of the memory controllers through a respective one of the first switch ports and to selectively couple each of the memory requesters to any one of the second switch ports; and a second rank of memory modules each of which comprise; a plurality of memory devices; and a memory hub comprising; a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices in the memory module; and a cross bar switch having a plurality of third switch ports and a plurality of memory ports, each of the third switch ports being coupled to one of the second switch ports in the memory hub in a respective one of the memory modules in the first rank, and each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the memory modules in the first plurality to any one of the memory controllers in the memory hub. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11)
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Specification