Methods and devices for treating and/or processing data

• US 7,581,076 B2
• Filed: 03/05/2002
• Issued: 08/25/2009
• Est. Priority Date: 03/05/2001
• Status: Expired due to Term

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US10/471,061
• Publication Number:
  US 20050086462A1
• Time in Patent Office: 2,730 Days
• Field of Search: None
• US Class Current: 711/202
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).

Claims

1. A method of transmitting data streams between (a) a reconfigurable processor device including an at least two-dimensional matrix of configurable elements having arithmetic logic units (ALUs) and (b) devices that are external to the reconfigurable processor device, the method comprising:

using at least one address generator, generating addresses according to which the external data streams are addressed; and

at least one of;

(a) buffering write data streams by storing output write addresses and corresponding output write data in a FIFO memory system; and

(b) buffering read data streams by storing output read addresses and input read data in the FIFO memory system.

2. The method as recited in claim 1, wherein a plurality of independent address generators are used.

3. The method as recited in claim 2, wherein the address generators are one of (a) configured independently of data processing and (b) hardwired.

4. The method as recited in claim 3 wherein address calculations for a plurality of configurations are determined at compile time prior to processing of data streams which occurs according to the compile.

5. The method as recited in claim 4, further comprising:

determining data that will be needed in future configurations that are executed; and

preloading respective data of the determined data into memories one of (a) prior to and (b) during the execution of respective ones of the future configurations.

6. The method as recited in claim 3, further comprising:

determining data that will be needed in future configurations that are executed; and

preloading respective data of the determined data into memories one of (a) prior to and (b) during the execution of respective ones of the future configurations.

7. The method as recited in claim 2, wherein address calculations for a plurality of configurations are determined at compile time prior to processing of data streams which occurs according to the compile.

8. The method as recited in claim 7, further comprising:

determining data that will be needed in future configurations that are executed; and

preloading respective data of the determined data into memories one of (a) prior to and (b) during the execution of respective ones of the future configurations.

9. The method as recited in claim 1, wherein address calculations for a plurality of configurations are determined at compile time prior to processing of data streams which occurs according to the compile.

10. The method as recited in claim 9, further comprising:

determining data that will be needed in future configurations that are executed; and

preloading respective data of the determined data into memories one of (a) prior to and (b) during the execution of respective ones of the future configurations.

11. The method as recited in claim 1, further comprising:

determining data that will be needed in future configurations that are executed; and

preloading respective data of the determined data into memories one of (a) prior to and (b) during the execution of respective ones of the future configurations.

12. The method as recited in claim 2, further comprising:

determining data that will be needed in future configurations that are executed; and

preloading respective data of the determined data into memories one of (a) prior to and (b) during the execution of respective ones of the future configurations.

13. The method as recited in claim 1, wherein:

at least one of the data streams is a stream of external data that is directed into the matrix array and is addressed to an element of the matrix array.

14. The method as recited in claim 1, wherein at least one of the data streams is a stream of external data directed away from the matrix array into a device different from the matrix array.

15. The method as recited in any one of claims 2 to 11 and 7 to 10, wherein:

data for an external data stream is generated by configured elements of the array, is stored in the FIFO memory, and remains stored in the FIFO memory while at least one of the elements of the array which generated the data is reconfigured; and

the method further comprises;

streaming data out of the FIFO memory as an external data stream to a receiver; and

receiving an acknowledgement of correct receipt of the data streamed to the receiver.

16. The method as recited in claim 15, further comprising:

preventing at least one of (a) erasure and (b) overwriting of the generated data stored in the FIFO memory if the generated data has been sent but receipt of the generated has not been acknowledged.