Memory controller for non-homogeneous memory system
First Claim
1. A controller, comprising:
- at least one interface adapted to be coupled to one or more first memory devices, comprising volatile memory devices, and one or more second memory devices, comprising non-volatile memory devices; and
interface logic coupled to the at least one interface to direct memory transactions having a predefined first characteristic to the first memory devices and to direct at least some memory transactions having a predefined second characteristic to the second memory devices, wherein the second characteristic comprises a usage characteristic selected from the group consisting of a read-mostly characteristic and read-only characteristic; and
wherein the usage characteristic of at least some memory transactions is updated during operation.
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Abstract
A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.
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Citations
25 Claims
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1. A controller, comprising:
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at least one interface adapted to be coupled to one or more first memory devices, comprising volatile memory devices, and one or more second memory devices, comprising non-volatile memory devices; and interface logic coupled to the at least one interface to direct memory transactions having a predefined first characteristic to the first memory devices and to direct at least some memory transactions having a predefined second characteristic to the second memory devices, wherein the second characteristic comprises a usage characteristic selected from the group consisting of a read-mostly characteristic and read-only characteristic; and
wherein the usage characteristic of at least some memory transactions is updated during operation. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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- 2. The controller of clam 1, wherein the second memory devices have a limited write operation endurance.
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11. A controller, comprising:
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interface means for coupling the controller to one or more first memory devices comprising volatile memory devices and to one or more second memory devices comprising non-volatile memory devices; and logic means coupled to the interface means for directing memory transactions having a predefined first characteristic to the first memory devices and for directing at least some memory transactions having a predefined second characteristic to the second memory devices, wherein the second characteristic comprises a usage characteristic selected from the group consisting of a read-mostly characteristic and read-only characteristic, and wherein the usage characteristic of at least some memory transactions is updated during operation.
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12. A system, comprising:
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at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes and to one or more second memory devices of a second memory type having a second set of attributes, wherein the first and second sets of attributes have at least one differing attribute; interface logic coupled to the at least one interface and configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices; and a processor having virtual memory logic for mapping virtual memory addresses into physical memory addresses and page logic for assigning physical memory addresses to virtual memory addresses, wherein the page logic is configured to assign physical memory addresses in the one or more first memory devices to virtual memory addresses associated with a first usage characteristic, and to assign physical memory addresses in the one or more second memory devices to virtual memory addresses associated with a second usage characteristic. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. The system, comprising:
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interface means for coupling to one or more first memory devices of a first memory type having a first set of attributes and to one or more second memory devices of a second memory type having a second set of attributes, wherein the first and second sets of attributes have at least one differing attribute; logic means coupled to the interface means for directing memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices; and virtual memory means for mapping virtual memory addresses into physical memory addresses and page means for assigning physical memory addresses to virtual memory addresses, wherein the page means assigned physical memory addresses in the one or more first memory devices to virtual memory addresses associated with a first usage characteristic, and assigns physical memory addresses in the one or more second memory devices to virtual memory addresses associated with a second usage characteristic.
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20. A method of managing memory in a non-homogeneous memory system, comprising:
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establishing a plurality of page table entries, each entry in the plurality of page table entries mapping a virtual memory page address to a physical memory page address, each said entry including a usage field identifying a respective portion of main memory in which the physical memory page address is located, wherein the main memory includes at least two distinct portions, including a first portion implemented with one or more first memory devices of a first memory type having a first set of attributes and a second portion implemented with one or more second memory devices of a second memory type having a second set of attributes, wherein the first and second sets of attributes have at least one differing attribute; receiving a memory transaction request; translating a virtual address of a page associated with the memory transaction request into a physical address in accordance with a corresponding page table entry of the plurality of page table entries, the physical address comprising a physical address in a respective portion of main memory; directing the memory transaction to the physical address in the respective portion of main memory. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification