Digital signal processor

• US 7,581,086 B2
• Filed: 02/26/2007
• Issued: 08/25/2009
• Est. Priority Date: 01/16/2007
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Huang, Po-Han, Peng, Chuan-Cheng
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US11/679,028
• Publication Number:
  US 20080172546A1
• Time in Patent Office: 911 Days
• Field of Search: 712/220
• US Class Current: 712/220
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/342 Extension of operand address space
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A digital signal processor is provided, comprising at least one cluster. The cluster may comprise at least two function units each conducting different instruction types, at least two private register files each associated with one function unit for data storage, a ping-pong register providing exclusively accessible data storage, and a public register file. The public register file comprises at least two read ports, each coupled to a function unit, providing read accessibility for the function units, and one write port to write data to the public register file.

Claims

1. A digital signal processor, comprising:

at least one cluster, comprising;

at least two function units, each conducting different type instructions, comprising a load/store unit for executing loading and storing instructions, and an arithmetic unit for performing arithmetic calculations, wherein the load/store unit and the arithmetic unit support pointer instructions;

two index register files respectively connected to the load/store unit and the arithmetic unit, each maintaining an index value and an offset value;

wherein each index register file updates the index value by adding the offset value to the index value after per read operation;

at least two private register files, individually connected to the load/store unit and the arithmetic unit for data storage;

a ping-pong register, connected to the load/store unit and the arithmetic unit for providing exclusively accessible data storage; and

a public register file, comprising;

two read ports, individually connected to the load/store unit and the arithmetic unit, allowing the load/store unit and the arithmetic unit to concurrently read same data from the public register file; and

one write port directly connected to the load/store unit, via which data is input and stored in the public register file.

2. The digital signal processor as claimed in claim 1, further comprising a data memory, accessible by the clusters via a memory interface unit.

3. The digital signal processor as claimed in claim 2, further comprising:

an instruction memory, storing different type instructions; and

a program controller, coupled to the instruction memory and the clusters, reading the instruction memory and dispatching the instructions to corresponding function units according to the instruction types.

4. The digital signal processor as claimed in claim 3, wherein:

one of the private register files connected to the load/store unit is an address register comprising a plurality of register cells for storage of parameters of the loading and storing instructions.

5. The digital signal processor as claimed in claim 3, wherein:

one of the private register files connected to the arithmetic unit is an accumulation register comprising a plurality of register cells for storage of parameters of the arithmetic calculations.

6. The digital signal processor as claimed in claim 3, wherein:

the ping-pong register comprise a plurality of register cells divided into a ping register and a pong register, providing accessibility for the function units in a swapping fashion;

when the load/store unit occupies the ping register, the arithmetic unit is inaccessible to the ping register; and

when the load/store unit occupies the pong register, the arithmetic unit is accessible to the ping register.