System for a memory device having a power down mode and method

• US 7,581,121 B2
• Filed: 06/14/2005
• Issued: 08/25/2009
• Est. Priority Date: 03/10/1998
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A., Davis, Paul G., Bystrom, Todd W., May, Bradley A.
• Primary Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US11/151,791
• Publication Number:
  US 20050235130A1
• Time in Patent Office: 1,533 Days
• Field of Search: 713/300, 713/323, 713/330, 711/167
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.

Claims

1. A system comprising:

a storage location to store information representing a timing parameter pertaining to a random access memory device; and

an integrated circuit device to generate a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command, the integrated circuit device to generate the value from the information representing the timing parameter pertaining to the random access memory device.

2. The system of claim 1, further including a memory module, wherein the storage location and the random access memory device are included on the memory module and wherein the integrated circuit device is a memory controller coupled to the memory module.

3. The system of claim 1, wherein the storage location is included in a serial presence detect.

4. The system of claim 3, further including the random access memory device, wherein the random access memory device includes:

a delay lock loop circuit to synchronize output of data with a clock signal; and

a first register to store first biasing information that is associated with a first time period during which the delay lock loop circuit acquires the clock signal while exiting the power down mode such that a first amount of functionality of the random access memory device is achieved, wherein the period of time that elapses before receiving the command includes the first time period.

5. The system of claim 4, wherein the random access memory device further includes a second register to store second biasing information that is associated with a second time period during which the delay lock loop circuit acquires the clock signal while exiting the power down mode such that a second amount of functionality of the random access memory device is achieved, wherein the period of time that elapses before receiving the command is an aggregate of the first time period and the second time period.

6. The system of claim 5, wherein the integrated circuit device receives information representative of the first time period and the second time period from the storage location, the first integrated circuit device to generate the value by dividing the information representative of the first time period and the second time period by a period of the clock signal to generate the value in terms of clock cycles of the clock signal.

7. The system of claim 6, wherein the integrated circuit device generates the value and rounds the value to terms of a next whole number of clock cycles of the clock signal when a fractional number of clock cycles results when dividing the period of time by the period of the clock signal.

8. A memory controller comprising:

an interface to provide a first value to a memory device, wherein the first value is representative of a period of time to elapse between the memory device exiting from a power down mode and a time at which the memory device is capable of receiving a command, wherein the first value is derived from parameter information that pertains to the memory device.

9. The memory controller of claim 8, wherein the interface provides to the memory device:

a second value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address, in response to the command, and an access of data sensed from a row of memory cells in a memory array of the memory device, wherein a location of the data is based on the column address; and

a third value that is representative of a number of clock cycles of the clock signal to elapse between the access of data sensed from the row of memory cells and the memory device outputting the data.

10. The memory controller of claim 8, wherein the memory device is included on a memory module, wherein the memory controller receives the parameter information from a storage device located on the memory module, wherein the parameter information includes:

information that represents a time to sense a row of the memory device;

information that represents a time between a row access operation of the memory device and a column access operation of the memory device;

information that represents a time between a row access operation of the memory device and a precharge operation of the memory device; and

information that represents a time between a row sense operation applied to a first bank of the memory device and a row sense operation applied to a second bank of the memory device.

11. The memory controller of claim 8, wherein the memory controller generates the first value by converting the parameter information of the memory device from units of time to units of clock cycles of the clock signal.

12. The memory controller of claim 8, wherein the memory controller is configured in accordance with the parameter information used to derive the first value.

13. The memory controller of claim 8, wherein, while in the power down mode, the memory device consumes less power than after exiting the power down mode.

14. A system comprising:

a storage location to store information representing a plurality of timing parameters pertaining to a random access memory device having a memory array, wherein the information includes information representing a first timing parameter; and

an integrated circuit device to receive the information representing the first timing parameter, the integrated circuit device to generate, using the information representing the first timing parameter, a value representative of a period of time that elapses before the random access memory device receives a read command once an instruction to exit the power down mode has been received by the random access memory device, wherein the read command instructs the random access memory device to output data.

15. The system of claim 14, wherein the integrated circuit device generates the value by converting the information representing the first timing parameter from units of time to units of clock cycles of a clock signal.

16. The system of claim 15, wherein converting includes dividing the information representing the first timing parameter in units of time by a period of the clock signal to generate the value and rounding the value to terms of a next whole number of clock cycles of the clock signal when a fractional number of clock cycles results when dividing the information representing the first timing parameter in units of time by the period of the clock signal.

17. The system of claim 14, wherein the storage location is included along with the random access memory device on a memory module.

18. The system of claim 14, wherein the storage location is a serial presence detect.

19. The system of claim 14, wherein the information representing the plurality of timing parameters includes:

information that represents a time to sense a row of the random access memory device;

information that represents a time between a row access operation of the random access memory device and a column access operation of the random access memory device;

information that represents a time between a row access operation of the random access memory device and a precharge operation of the random access memory device;

information that represents a time between a row sense operation applied to a first bank of the random access memory device and a row sense operation applied to a second bank of the random access memory device; and

information that represents a time between a precharge operation applied to a first bank of the random access memory device and a precharge operation applied to a second bank of the random access memory device.

20. The system of claim 14, wherein the integrated circuit device is configured in accordance with the information representing the first timing parameter.

21. The system of claim 14, wherein, while in the power down mode, the random access memory device consumes less power than after exiting the power down mode.