Interface circuit system and method for performing power saving operations during a command-related latency
First Claim
Patent Images
1. A memory apparatus for use with a system, the memory apparatus comprising:
- a plurality of memory circuits;
an interface circuit coupled to communicate with the memory circuits, and for communicating with the system, the interface circuit operable to perform a power management operation on at least a portion of the memory circuits during a latency associated with a command directed to at least a portion of the memory circuits.
3 Assignments
0 Petitions
Accused Products
Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.
643 Citations
26 Claims
-
1. A memory apparatus for use with a system, the memory apparatus comprising:
-
a plurality of memory circuits; an interface circuit coupled to communicate with the memory circuits, and for communicating with the system, the interface circuit operable to perform a power management operation on at least a portion of the memory circuits during a latency associated with a command directed to at least a portion of the memory circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
-
-
22. A method of operating a physical memory apparatus, the physical memory apparatus including a plurality of memory circuits and an interface circuit coupled to the plurality of physical memory circuits, the interface circuit further being coupled to a system which issues a command directed to at least a portion of the memory apparatus, the method comprising:
-
receiving the command; and during a latency associated with the command, performing a power management operation on at least a portion of the physical memory circuits. - View Dependent Claims (23, 24)
-
-
25. A memory apparatus for use with a system which issues a command having a latency determined by a first latency of the memory apparatus, the memory apparatus comprising:
-
a plurality of physical memory circuits having a second latency; and an interface circuit coupled to the plurality of physical memory circuits and couplable to the system, for simulating a memory having a the first latency which is different than the second latency, and for informing the system of the first latency, and for performing a power management operation on at least a portion of the physical memory circuits during the first latency. - View Dependent Claims (26)
-
Specification