Electronic packaging materials for use with low-k dielectric-containing semiconductor devices

• US 7,582,510 B2
• Filed: 11/09/2004
• Issued: 09/01/2009
• Est. Priority Date: 11/10/2003
• Status: Expired due to Fees

• Current Assignee: Henkel Corporation (Henkel AG & Co KGaA)
• Original Assignee: Henkel Corporation (Henkel AG & Co KGaA)
• Inventors: Huneke, James T., Fischer, Gordon C., Todd, Michael G., Crane, Lawrence N.
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US10/595,736
• Publication Number:
  US 20080122088A1
• Time in Patent Office: 1,757 Days
• Field of Search: 438106-109, 438121-127, 438/E23.001, 438/E23.121
• US Class Current: 438/106
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 : Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

Electronic packaging materials for use with Low-k dielectric-containing semiconductor devices are provided.

Claims

1. A method of improving reliability of a semiconductor device comprising at least one layer of low-K ILD, steps of which comprise:

providing a semiconductor device comprising;

a semiconductor chip comprising copper electrical interconnections and at least one layer of low-K ILD therewithin and metallization on a surface thereof; and

a carrier substrate having electrical contact pads on a surface thereof to which the semiconductor chip is electrically interconnected through an electrically conductive material to the copper electrical interconnections; and

optionally, a second semiconductor chip having opposed surfaces, one of which for bonding to the carrier substrate and the other of which for establishing electrical interconnection with both the semiconductor chip and the carrier substrate, wherein the carrier substrate has electrical contact pads on a surface thereof to which at least one of the semiconductor chip or the second semiconductor chip is electrically interconnected;

providing a heat curable composition either between the electrically interconnected surfaces of the semiconductor chip and the carrier substrate to form a semiconductor device assembly and/or over the semiconductor device assembly; and

exposing the semiconductor device assembly to elevated temperature conditions sufficient to cure the heat curable composition,

wherein the heat curable composition comprises a curable resin component and a filler component, wherein the filler component is present in an amount sufficient to provide the heat curable composition when cured with a coefficient of thermal expansion of less than about 25 ppm/°

C. or a coefficient of thermal expansion of greater than about 50 ppm/°

C. and when cured the heat curable composition has a ratio of modulus versus temperature between −

65°

C. and 125°

C. in the range of 10 MPa/°

C. to about −

10 MPa/°

C.

2. The method of claim 1, wherein the electrically conductive material is solder.

3. The method of claim 2, wherein the solder is selected from the group consisting of Sn(63):

Pb(37), Pb(95);

Sn(5), Sn;

Ag(3.5);

Cu(0.5) and Sn;

Ag(3.3);

Cu(0.7).

4. An underfilled semiconductor device assembly comprising:

Either a semiconductor chip comprising copper electrical interconnection and the layer of low-K ILD therewithin and metallization on a surface thereof or a semiconductor device comprising a semiconductor chip comprising copper electrical interconnection thereof contacting at least one layer of low-K ILD therewithin and metallization on a surface thereof to which is electrically connected a carrier substrate;

a circuit board having electrical contact pads on a surface thereof to which the semiconductor chip or semiconductor device, respectively, is electrically interconnected; and

a heat curable underfill composition between the semiconductor chip or semiconductor device, respectively, and the circuit board,

wherein the heat curable underfill composition comprises a curable resin component and a filler component, wherein the filler component is present in an amount sufficient to provide the heat curable underfill composition when cured with a coefficient of thermal expansion of less than about 25 ppm/°

C. or a coefficient of thermal expansion of greater than about 50 ppc/°

C., and wherein the heat curable underfill composition has a ratio of modulus versus temperature between −

65°

C. and 125°

C. in the range of −

10 MBa/°

C. to about 10 MPa/°

C.

5. The device of claim 4, wherein the electrically conductive material is solder.

6. The method of claim 5, wherein the solder is selected from the group consisting of Sn(63):

Pb(37), Pb(95);

Sn(5), Sn;

Ag(3.5);

Cu(0.5) and Sn;

Ag(3.3);

Cu(0.7).

7. A method of assembling a semiconductor device with improved reliability, steps of which comprise:

providing a semiconductor chip having opposed surfaces, one of which for bonding to a carrier substrate and the other of which having electrical interconnections for establishing electrical interconnection therewith, and having a thickness of less than 100 microns;

providing a carrier substrate having a portion of a surface for bonding the semiconductor chip and another portion of a surface for establishing electrical interconnection with the semiconductor chip;

providing a heat curable die attach composition onto at least a portion of one or both of the bonding surface of the semiconductor chip or the bonding surface of the carrier substrate, in an amount sufficient to establish a bondline of less than about 10 microns when the semiconductor chip and the carrier substrate are mated;

mating the bonding surface of the semiconductor chip with the bonding surface of the carrier substrate to form a semiconductor device assembly and exposing the semiconductor device assembly to elevated temperature conditions sufficient to cure the heat curable die attach composition, thereby bonding the semiconductor device to the carrier substrate; and

establishing electrical interconnections between the semiconductor device and the carrier substrate,

wherein when cured the heat curable die attach composition has a ratio of modulus versus temperature between −

65°

C. and 125°

C. in the range of −

10 MPa/°

C. to about −

10 MPa/°

C.

8. The method of claim 7, wherein the heat curable die attach composition comprises a curable resin component and a tiller component, wherein the filler component is present in an amount sufficient to provide the hear curable die attach composition when cured with a coefficient of thermal expansion of less than about 25 ppm/°

C. or a coefficient of thermal expansion of greater than about 50 ppm/°

C.

10. The method of claim 7, wherein the electrical interconnection is established through an electrically conductive material.

11. The method of claim 10, wherein the electrically conductive material is solder.

12. The method of claim 11, wherein the solder is selected from the group consisting of Sn(63):

Pb(37), Pb(95);

Sn(5), Sn;

Ag(3.5);

Cu(0.5) and Sn;

Ag(3.3);

Cu(0.7).

9. A semiconductor device comprising:

a semiconductor chip having opposed surfaces, one of which for bonding to a carrier substrate and the other of which having electrical interconnections for establishing electrical interconnection therewith, and having a thickness of less than 100 microns;

a carrier substrate having a portion of a surface for bonding the semiconductor chip and another portion of a surface for establishing electrical interconnection with the semiconductor chip; and

a die attach composition between the bonding surfaces of the semiconductor chip and the carrier substrate, to form a bond line of less than about 10 microns,

wherein the die attach composition has a ratio of modulus versus temperature between −

65°

C. and 125°

C. in the range of 10 MPa/°

C. to about 10 MPa/°

C.