High performance device design

• US 7,582,947 B2
• Filed: 10/05/2005
• Issued: 09/01/2009
• Est. Priority Date: 10/05/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Fu-Liang, Huang, Chien-Chao
• Primary Examiner(s): Luu; Chuong A.
• Application Number:
  US11/243,959
• Publication Number:
  US 20070075377A1
• Time in Patent Office: 1,427 Days
• Field of Search: 257/374, 257/510, 257/288, 257/249, 257/368, 257/387, 257/365, 257/366, 257/331, 257/153
• US Class Current: 257/510
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356

Abstract

A semiconductor structure having a recessed active region and a method for forming the same are provided. The semiconductor structure comprises a first and a second isolation structure having an active region therebetween. The first and second isolation structures have sidewalls with a tilt angle of substantially less than 90 degrees. The active region is recessed. By recessing the active region, the channel width is increased and device drive current is improved.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a first and a second isolation region disposed in the substrate and defining a first active region in the semiconductor substrate therebetween, wherein the first and second isolation region have sidewalls with a tilt angle of substantially less than about 90 degrees;

a gate dielectric in the first active region and over the semiconductor substrate;

a gate electrode over the gate dielectric;

a source/drain region substantially aligned with a sidewall of the gate electrode;

a second active region in the semiconductor substrate, wherein the second active region has a top surface higher than a top surface of the first active region by a height difference of at least about 100 Å

;

an additional gate dielectric in the second active region and over the semiconductor substrate;

an additional gate electrode over the additional gate dielectric; and

an additional source/drain region substantially aligned with a sidewall of the additional gate electrode.

2. The semiconductor structure of claim 1, wherein the first active region has a substantially rounded surface.

3. The semiconductor structure of claim 1, wherein the height difference is between about 100 Å

and about 1000 Å

.

4. The semiconductor structure of claim 1, wherein the height difference is greater than about 20 percent of a depth of the first and second isolation structures.

5. The semiconductor structure of claim 1, wherein the first and second isolation structures are shallow trench isolation regions.

6. The semiconductor structure of claim 1, wherein the tilt angle is less than about 85 degrees.

7. The semiconductor structure of claim 1, wherein the tilt angle is less than about 75 degrees.

8. The semiconductor structure of claim 1, wherein the first active region is a core device region and the second active region is a peripheral device region.

9. The semiconductor structure of claim 2, wherein the substantially rounded surface comprises a central portion, and edge portions surrounding the central portion, and wherein the central portion is higher than the edge portions.

10. The semiconductor structure of claim 9, wherein the top surface of the second active region is substantially planar.

11. A semiconductor structure comprising:

a semiconductor substrate;

a first and a second isolation structure in the semiconductor substrate and having a first active region therebetween, wherein the first and the second isolation structures have sidewalls with a tilt angle of less than about 85 degrees;

a third and a fourth isolation structure in the semiconductor substrate and having a second active region therebetween, wherein the second active region is higher than the first active region for a height difference greater than about 100 Å

;

a first gate dielectric in the first active region and over the semiconductor substrate;

a first gate electrode over the first gate dielectric; and

a first source/drain region substantially aligned with a sidewall of the first gate electrode.

12. The semiconductor structure of claim 11, wherein the height difference is between about 100 Å

and about 1000 Å

.

13. The semiconductor structure of claim 11, wherein the height difference is greater than about 20 percent of a depth of the first and second isolation structures.

14. The semiconductor structure of claim 11 further comprising:

a second gate dielectric in the second active region and over the semiconductor substrate;

a second gate electrode over the second gate dielectric; and

a second source/drain region substantially aligned with a sidewall of the second gate electrode.

15. The semiconductor structure of claim 11, wherein the first and second isolation structures are shallow trench isolations.

16. The semiconductor structure of claim 11, wherein the first active region is a core device region and the second active region is an I/O device region.

17. The semiconductor structure of claim 11, wherein a top surface of the first active region comprises a central portion, and edge portions surrounding the central portion, and wherein the central portion is higher than the edge portions.

18. The semiconductor structure of claim 17, wherein a top surface of the second active region is substantially planar.