Method and system for digitally controlling transmitter gain compensation

• US 7,583,143 B2
• Filed: 12/28/2006
• Issued: 09/01/2009
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Pan, Meng-An
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): Nguyen; Hieu P
• Application Number:
  US11/617,458
• Publication Number:
  US 20080136520A1
• Time in Patent Office: 978 Days
• Field of Search: 330/254, 330/305, 330/278
• US Class Current: 330/254
• CPC Class Codes: H03G 1/0035 using continuously variable impedance elements

Abstract

Methods and systems for digitally controlling transmitter gain compensation are disclosed. Aspects of one method may include applying an effective negative resistance to differential outputs of amplifying circuitry to compensate for gain changes that may be due to temperature changes. The effective negative resistance may be provided via a plurality of load circuits coupled in parallel to the differential outputs. The plurality of load circuits may have similar effective negative resistances, or the plurality of load circuits may be binary weighted. Each load circuit may be selected via digital control signals that may enable the load circuit. This may allow adjusting of the effective negative resistance by selecting different load circuits.

Claims

1. A method for processing signals, the method comprising:

digitally controlling selection of each of a plurality of load circuits to apply an effective negative resistance to differential outputs of amplifying circuitry to compensate for gain changes in said amplifying circuitry.

2. The method according to claim 1, comprising providing said effective negative resistance with said plurality of load circuits directly electrically coupled in parallel to said differential outputs.

3. The method according to claim 2, wherein said plurality of load circuits have similar said effective negative resistances.

4. The method according to claim 2, comprising weighting said effective negative resistance of each of said plurality of load circuits.

5. The method according to claim 4, wherein said weighting is a binary weighting.

6. The method according to claim 2, comprising digitally controlling selection of each of said plurality of load circuits to adjust said effective negative resistance.

7. The method according to claim 1, comprising adjusting said effective negative resistance as temperature of a portion of chip comprising said amplifying circuitry changes.

8. A machine-readable storage having stored thereon, a computer program having at least one code section for processing signals, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

digitally controlling selection of each of a plurality of load circuits to apply an effective negative resistance to differential outputs of amplifying circuitry to compensate for gain changes in said amplifying circuitry.

9. The machine-readable storage according to claim 8, wherein the at least one code section comprises code for providing said effective negative resistance with said plurality of load circuits directly electrically coupled in parallel to said differential outputs.

10. The machine-readable storage according to claim 9, wherein said plurality of load circuits have similar said effective negative resistances.

11. The machine-readable storage according to claim 9, wherein the at least one code section comprises code for weighting said effective negative resistance of each of said plurality of load circuits.

12. The machine-readable storage according to claim 11, wherein said weighting is a binary weighting.

13. The machine-readable storage according to claim 9, wherein the at least one code section comprises code for digitally controlling selection of each of said plurality of load circuits to adjust said effective negative resistance.

14. The machine-readable storage according to claim 8, wherein the at least one code section comprises code for adjusting said effective negative resistance as temperature of a portion of chip comprising said amplifying circuitry changes.

15. A system for processing signals, the system comprising:

one or more circuits that enables digital control of selection of each of a plurality of load circuits to apply an effective negative resistance to differential outputs of amplifying circuitry to compensate for gain changes in said amplifying circuitry.

16. The system according to claim 15, wherein said load block comprises said plurality of load circuits directly electrically coupled in parallel to said differential outputs.

17. The system according to claim 16, wherein said plurality of load circuits have similar said effective negative resistances.

18. The system according to claim 16, wherein said effective negative resistance of each of said plurality of load circuits is weighted.

19. The system according to claim 18, wherein said weighting is a binary weighting.

20. The system according to claim 16, wherein each of said plurality of load circuits is digitally controlled to adjust said effective negative resistance.

21. The system according to claim 15, comprising one or both of a processor and circuitry that enables adjusting said effective negative resistance as temperature of a portion of chip comprising said amplifying circuitry changes.