Multi-protocol radio frequency identification transceiver

• US 7,583,179 B2
• Filed: 06/16/2005
• Issued: 09/01/2009
• Est. Priority Date: 02/22/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wu, Jiangfeng, Major, Donald Edward
• Primary Examiner(s): Zimmerman; Brian A
• Assistant Examiner(s): Jiang; Yong Hang
• Application Number:
  US11/154,231
• Publication Number:
  US 20060186995A1
• Time in Patent Office: 1,538 Days
• Field of Search: 340/10.1, 340/572.1, 340/572.4, 340/10.4, 375/329
• US Class Current: 340/10.1
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04B 1/408 the transmitter oscillator frequency being identical to the receiver local oscillator frequency

Abstract

A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.

Claims

1. An apparatus comprising:

a transmitter to transmit a radio frequency identification (RFID) signal to a RFID transponder; and

a receiver to receive a RFID reply signal from the RFID transponder, demodulate the received signal in an analog front end that includes a local oscillator and at least one mixer for demodulation of the received signal, convert the received signal from an analog form into a digital signal, and process the digital signal in a digital back end, in which the digital back end includes a digital signal processor (DSP) to process the digital signal and in which the DSP includes a filter decimator to provide low-pass filtering on an oversampled data stream of the digital signal and decimation to a lower frequency, a band-pass filter to eliminate noise and interference outside a signal bandwidth, a matched filter in combination with a programmable sequence generator that is programmable with protocol-specific sequences to compute correlations between the digital signal and the protocol-specific sequences each corresponding to a particular RFID communication protocol, a power estimator to measure estimation of the correlations, a data slicer to recover data and a collision detector to detect collisions when collisions occur in the data recovery, wherein the transmitter and the receiver, including the DSP, are manufactured on a single complementary metal-oxide semiconductor (CMOS) integrated circuit chip and the matched filter and the programmable sequence generator are programmable to accommodate multiple RFID protocols to be processed by the matched filter.

2. The apparatus of claim 1 wherein the transmitter further includes an analog antenna end and a digital processing end and in which the analog antenna end of the transmitter receives data to be transmitted from the digital processing end and modulates a carrier to transmit the RFID signal.

3. The apparatus of claim 2 wherein the transmitter further includes a digital signal processor in the transmitter digital processing end.

4. The apparatus of claim 1 further including an attenuator at an input of the receiver to attenuate the received signal.

5. The apparatus of claim 4 wherein the attenuator is programmable to change an amount of attenuation of the received signal.

6. A radio frequency identification (RFID) reader receiver comprising:

an analog front end including a local oscillator and at least one mixer to demodulate an incoming RFID signal;

an analog-to-digital convener (ADC) to convert the demodulated RFTD signal into a digital signal; and

a digital back end including a digital signal processor (DSP) to process the digital signal and in which the DSP includes a filter decimator to provide low-pass filtering on an oversampled data stream of the digital signal and decimation to a lower frequency, a band-pass filter to eliminate noise and interference outside a signal bandwidth, a matched filter in combination with a programmable sequence generator that is programmable with protocol-specific sequences to compute correlations between the digital signal and the protocol-specific sequences each corresponding to a particular RFID communication protocol, a power estimator to measure estimation of the correlations, a data slicer to recover data and a collision detector to detect collisions when collisions occur in the data recovery, wherein the analog front end, ADC and the digital back end, including the DSP, are manufactured on a single complementary metal-oxide semiconductor (CMOS) integrated circuit chip and the matched filter and the programmable sequence generator are programmable to accommodate multiple RFID protocols to be processed by the matched filter.

7. The RFID reader of claim 6 further including an attenuator at an input of the analog front end to attenuate the incoming RFID signal.

8. The RFID reader of claim 7 wherein the attenuator is programmable to change an amount of attenuation of the incoming RFJD signal.

9. The RFID reader of claim 6 wherein the analog front end to use direct conversion architecture with quadrature demodulation.

10. The RFID reader of claim 9 wherein the analog front end includes a pair of down-conversion mixers, a pair of band-pass filters and a pair of programmable gain amplifiers.

11. The RFID reader of claim 10 wherein the analog front end includes switched capacitor circuits.

12. The RFID reader of claim 6 wherein the DSP includes a cascaded integrator-comb filter/decimator to provide low-pass filtering of the oversampled data stream from the ADC and to filter and decimate to the lower frequency.

13. The RFID reader of claim 12 further including a finite impulse response filter for the band-pass filter.

14. A method comprising:

receiving an incoming radio frequency identification (RFID) signal at an analog front end of a RFID reader that includes a local oscillator and at least one mixer for demodulation of the received RFID signal;

demodulating the received RFID signal by down conversion;

converting the demodulated RFID signal into a digital signal; and

processing the digital signal at a back end of the RFID receiver using digital signal processing in a digital signal processor (DSP), in which the DSP includes a filter decimator to provide low-pass filtering on an oversampled data stream of the digital signal and decimation to a lower frequency, a band-pass filter to eliminate noise and interference outside a signal bandwidth, a matched filter in combination with a programmable sequence generator that is programmable with protocol-specific sequences to compute correlations between the digital signal and the protocol-specific sequences each corresponding to a particular RFID communication protocol, a power estimator to measure estimation of the correlations, a data slicer to recover data and a collision detector to detect collisions when collisions occur in the data recovery, wherein the demodulating, convening and processing using DSP are performed by components manufactured on a single complementary metal-oxide semiconductor (CMOS) integrated circuit chip and wherein the matched filter and the programmable sequence generator are programmable to accommodate multiple RFID protocols to be processed by the matched filter.

15. The method of claim 14 further comprising attenuating the incoming RFID signal to make the incoming signal level compatible with CMOS integrated circuit components.

16. The method of claim 14 further including performing an analog signal processing at the analog front end by use of a switched capacitor circuit on a sampled RFID signal.