Nonvolatile semiconductor memory device
First Claim
1. A nonvolatile semiconductor memory device comprising:
- a unit block cell array including a plurality of vertically layered cell arrays including a plurality of unit cells arranged in row and column directions;
a column address decoder configured to decode a column address to activate a bit line of a cell array selected from the plurality of cell arrays;
a sense amplifier unit configured to sense and amplify data of the bit line of the plurality of cell arrays and shared by the unit block cell array; and
a vertical address decoding unit configured to decode a vertical address to select one of the plurality of cell arrays and to connect an output signal from the sense amplifier to the bit line of the selected cell array;
wherein the plurality of cell arrays comprise;
a plurality of bottom word lines;
an insulating layer formed over the plurality of bottom word lines;
a floating channel layer formed over the insulating layer and including a plurality of drain and source regions serially connected to a plurality of channel regions alternately;
a ferroelectric layer formed over the floating channel layer; and
a plurality of word lines formed over the ferroelectric layer so as to be connected to the plurality of bottom word lines,wherein a different resistance is induced to a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so that data is read or written.
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Abstract
A nonvolatile semiconductor memory device includes a plurality of 3-dimensional cell arrays to reduce the chip size. The nonvolatile semiconductor memory device includes a unit block cell array including a plurality of vertically multi-layered cell arrays each including a plurality of unit cells arranged in row and column directions, a column address decoder configured to decode a column address to activate a bit line of the selected cell array from the plurality of cell arrays, a sense amplifier unit configured to sense and amplify data of the bit line of the plurality of cell arrays and shared by the unit block cell array, and a vertical address decoding unit configured to decode a vertical address to select one of the plurality of cell arrays and to connect an output signal from the sense amplifier to the bit line of the selected cell array.
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Citations
19 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a unit block cell array including a plurality of vertically layered cell arrays including a plurality of unit cells arranged in row and column directions; a column address decoder configured to decode a column address to activate a bit line of a cell array selected from the plurality of cell arrays; a sense amplifier unit configured to sense and amplify data of the bit line of the plurality of cell arrays and shared by the unit block cell array; and a vertical address decoding unit configured to decode a vertical address to select one of the plurality of cell arrays and to connect an output signal from the sense amplifier to the bit line of the selected cell array; wherein the plurality of cell arrays comprise; a plurality of bottom word lines; an insulating layer formed over the plurality of bottom word lines; a floating channel layer formed over the insulating layer and including a plurality of drain and source regions serially connected to a plurality of channel regions alternately; a ferroelectric layer formed over the floating channel layer; and a plurality of word lines formed over the ferroelectric layer so as to be connected to the plurality of bottom word lines, wherein a different resistance is induced to a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so that data is read or written. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification