×

Nonvolatile semiconductor memory device

  • US 7,583,524 B2
  • Filed: 12/28/2006
  • Issued: 09/01/2009
  • Est. Priority Date: 12/30/2005
  • Status: Active Grant
First Claim
Patent Images

1. A nonvolatile semiconductor memory device comprising:

  • a unit block cell array including a plurality of vertically layered cell arrays including a plurality of unit cells arranged in row and column directions;

    a column address decoder configured to decode a column address to activate a bit line of a cell array selected from the plurality of cell arrays;

    a sense amplifier unit configured to sense and amplify data of the bit line of the plurality of cell arrays and shared by the unit block cell array; and

    a vertical address decoding unit configured to decode a vertical address to select one of the plurality of cell arrays and to connect an output signal from the sense amplifier to the bit line of the selected cell array;

    wherein the plurality of cell arrays comprise;

    a plurality of bottom word lines;

    an insulating layer formed over the plurality of bottom word lines;

    a floating channel layer formed over the insulating layer and including a plurality of drain and source regions serially connected to a plurality of channel regions alternately;

    a ferroelectric layer formed over the floating channel layer; and

    a plurality of word lines formed over the ferroelectric layer so as to be connected to the plurality of bottom word lines,wherein a different resistance is induced to a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so that data is read or written.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×