Router using clock synchronizer for distributed traffic control

• US 7,583,683 B2
• Filed: 05/09/2005
• Issued: 09/01/2009
• Est. Priority Date: 05/17/2004
• Status: Expired due to Fees

• Current Assignee: Yang Soon Cha
• Original Assignee: Yang Soon Cha
• Inventors: Kim, Kicheon
• Primary Examiner(s): Afshar; Kamran
• Application Number:
  US11/125,025
• Publication Number:
  US 20050254480A1
• Time in Patent Office: 1,576 Days
• Field of Search: 455/428, 455/455, 455/560, 455/502, 370/238, 370351-356, 370/389, 370/396, 370/395, 370/42, 370411-419, 370428-429, 370/503, 370/235, 370/401, 370/509, 370/350, 709202-205, 714/39, 710/1, 710/58, 710/61
• US Class Current: 370/401
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 45/60 Router architectures

Abstract

A router using distributed processing for FIB look-up and fair queuing algorithm is invented. The real-time traffic includes voice and video and should be transmitted in a certain time limit. Otherwise, the quality of the traffic is affected and the information is no longer useful. Packet scheduler in the router transmits packets within the time limit. However, the packet scheduler is not fast enough compared to the link speed and the size of the router. This invention uses a plurality of processors and almost identical time for each processor. FIB look-up and switching are performed by different processors to reduce the processing time. The traffic control algorithm can be performed independently by each processor. Thus, the processing speed of the entire router can be raised.

Claims

1. A router including processors or processing elements in line interface modules and a switching module, wherein the processor or processing element in each line interface module looks up a FIB (Forward Information Base) to determine a output port number for each arriving packet and sends the packet to the switching module after recording the output port number on a temporary packet header and a switching and queuing processor in the switching module sends the packets arriving from the line interface modules to an output queue connected to the destination line interface module according to the output port number field on the temporary packet header, additionally including a clock synchronizer, wherein the clock synchronizer makes the time of each module almost identical by providing common clock and reset signals to the line interface and switching modules;

wherein the clock synchronizer relates the period of the reset signal to a maximum packetization period of the real-time traffic.

2. A router including processors or processing elements in line interface modules and a switching module, wherein the processor or processing element in each line interface module looks up a FIB (Forward Information Base) to determine a output port number for each arriving racket and sends the racket to the switching module after recording the output port number on a temporary racket header and a switching and queuing processor in the switching module sends the rackets arriving from the line interface modules to an output queue connected to the destination line interface module according to the output port number field on the temporary racket header, further comprising a VLSI (Very Large Scale Integration) chip including plural processing elements, connected to the switching module including the switching and queuing processor, wherein the processing element looks up the FIB (Forward Information Base) to determine the output port number for each arriving packet and sends the packet to the switching module after recording the output port number on the temporary packet header and the switching and queuing processor in the switching module sends the packets arriving from the line interface modules to the output queue connected to the destination line interface module according to the output port number field on the temporary packet header.

3. A router including processors or processing elements in line interface modules and a switching module, wherein the processor or processing element in each line interface module looks up a FIB (Forward Information Base) to determine a output port number for each arriving racket and sends the racket to the switching module after recording the output port number on a temporary racket header and a clock synchronizer, wherein the router performs real-time traffic control based on common synchronized time provided by the clock synchronizer, using virtual finish time calculation algorithm for packet fair queuing using time from a timer of a clock synchronizer by adding the larger between the packet arrival time obtained from the clock synchronizer (Ai) and the virtual finish time of the previous packet (Fi−

1) to the packet length (Li) divided by the reserved rate (R);

Fi=max(Ai, Fi−

1)+Li/R.

4. A VLSI (Very Large Scale Integration) chip including plural processing elements, connected to a switching module which includes a switching and queuing processor, wherein the processing element looks up the FIB (Forward Information Base) to determine a output port number for each arriving packet and sends a packet to the switching module after recording the output port number on a temporary packet header and a switching and queuing processor in the switching module sends the packets arriving from the line interface modules to the output queue connected to the destination line interface module according to the output port number field on the temporary packet header.