Method and apparatus for extending processing time in one pipeline stage

• US 7,584,446 B2
• Filed: 04/27/2006
• Issued: 09/01/2009
• Est. Priority Date: 02/16/1999
• Status: Expired due to Fees

• Current Assignee: Dario B. Crosetto
• Original Assignee: Dario B. Crosetto
• Inventors: Crosetto, Dario B.
• Primary Examiner(s): Siek; Vuthe
• Assistant Examiner(s): BOWERS, BRANDON
• Application Number:
  US11/414,652
• Publication Number:
  US 20060259889A1
• Time in Patent Office: 1,223 Days
• Field of Search: 716/1, 716/10, 716/16
• US Class Current: 716/100
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

A single channel or multi-channel system that requires the execution time of a pipeline stage to be extended to a time longer than the time interval between two consecutive input data. Each processor in the system has an input and output port connected to a “bypass switch” (or multiplexer). Input date is sent either to a processor, for processing, or to a processor output port, in which case no processing is performed, through a register using at least one clock cycle to move date from register input to register output. For a single channel requiring an execution time twice the time interval between two consecutive input data, two processors are interconnected by the bypass switch. Data flows from the first processor at the input of the system, through the bypass switches of the interconnected processors, to the output. The bypass switches are configures with respect to the processors such that the system data rate is independent of processor number.

Claims

1. A system for processing data signals, comprising:

N processing units organized in series in a pipeline arrangement with an input end and an output end, wherein said pipeline arrangement receives data at said input end in a first time interval t1, wherein said N processing units comprises one or more repeating processing units and a non-repeating processing unit, and wherein each processing unit in said one or more repeating processing units comprises;

(A) a processor for receiving and transforming a first type of data signal into a second type of data signal,

wherein said processor has an input port for receiving said first type of data signal and an output port for sending said second type of data signal,

wherein said processor completes a predetermined algorithm in a second time interval t2, and wherein t2 is greater than t1, and

wherein N is an integer determined by said first time interval t1 and said second time interval t2,

wherein

$N=\frac{t<br><br><br><br>2}{t<br><br><br><br>1}$

 

when the ratio of said second time interval t2 to said first time interval t1,

$\frac{t<br><br><br><br>2}{t<br><br><br><br>1},$

 

is an integer, or

$N=\left(\left[\frac{t<br><br><br><br>2}{t<br><br><br><br>1}\right]+1\right)$

 

when said ratio

$\left(\frac{t<br><br><br><br>2}{t<br><br><br><br>1}\right)$

 

is not an integer, wherein [t2/t1] denotes the greatest integer less than or equal to

$\frac{t<br><br><br><br>2}{t<br><br><br><br>1};<br><br>$

(B) a register for storing said first type of data signal or said second type of data signal, wherein said second type of data signal is transformed by said processor from said first type of data signal according to said pre-determined algorithm;

(C) a bypass switch capable of being in a first state or a second state and operating in a plurality of cycles with each cycle in said plurality of cycles consisting of N consecutive first time intervals,

wherein, when in said first state, said bypass switch is connected to a register in an adjacent processing unit in said pipeline arrangement and to said register of (B), said processor of (A) is bypassed and does not receive said first type of data signal,

wherein, when in said second state, said bypass switch is not connected to any register in said pipeline arrangement, said input port of said processor of (A) is connected to a register in an adjacent processing unit in said pipeline arrangement and said output port of said processor of (A) is connected to said register of (B), and during said second state of said bypass switch, said processor of (A) receives a first type of data signal at said input port, and

wherein said cycle of N consecutive first time intervals consists of (i) N-1 consecutive first time intervals during which said bypass switch is in said first state and (ii) one first time interval during which said bypass switch is in said second state;

wherein, at any first time interval, only the bypass switch in one processing unit of said N processing units is in said second state, and

wherein said non-repeating processing unit comprises a processor, a register, and a bypass switch.

2. The system of claim 1, wherein said non-repeating processing unit is a starting processing unit which receives data from a data input device in said first time interval t1, and wherein said starting processing unit comprises:

(SA) a starting processor for receiving and transforming a first type of data signal into a second type of data signal,

wherein said starting processor has a starting input port for receiving said first type of data signal and a starting output port for sending said second type of signal,

wherein said starting processor completes said predetermined algorithm at said second time interval t2, and

wherein N is an integer determined by said first time interval t1 and said second time interval t2,

wherein

$N=\frac{t<br><br><br><br>2}{t<br><br><br><br>1}$

 

when the ratio of said second time interval t2 to said first time interval t1,

$\frac{t<br><br><br><br>2}{t<br><br><br><br>1},$

 

is an integer, or

$N=\left(\left[\frac{t<br><br><br><br>2}{t<br><br><br><br>1}\right]+1\right)$

 

when said ratio

$\left(\frac{t<br><br><br><br>2}{t<br><br><br><br>1}\right)$

 

is not an integer, wherein

$\left[\frac{t<br><br><br><br>2}{t<br><br><br><br>1}\right]$

 

denotes the greatest integer less than or equal to

$\frac{t<br><br><br><br>2}{t<br><br><br><br>1};<br><br>$

(SB) a starting register for storing said first type of data signal or said second type of data signal, wherein said second type of data signal is transformed by said staffing processor of (SA) from said first type of data signal according to said pre-determined algorithm;

(SC) a starting bypass switch having a first state and a second state and operating in cycles with each cycle consisting of N consecutive first time intervals,

wherein, when in said first state, said staffing bypass switch is connected to said data input device and to said staffing register of (SB), said staffing processor of (SA) is bypassed and does not receive said first type of data signal,

wherein, when in said second state, said starting bypass switch is not connected to said data input device or to said staffing register of (SA), said input port of said starting processor of (SA) is connected to said data input device and said output port of said staffing processor (SA) is connected to said staffing register of (SB), and during said second state of said staffing bypass switch, said starting processor of (SA) receives a first type data signal from said data input device at the staffing input port, and

wherein said cycle of N consecutive first time intervals consists of (i) N-1 consecutive first time intervals during which said staffing bypass switch is in said first state and (ii) one first time interval during which said staffing bypass switch is in said second state.

3. The system of claim 1, wherein said first type of data signal comprises a signal received from a sensor.

4. The system of claim 1, wherein N is an integer equal or greater than 2.

5. The system of claim 1, wherein N is an integer equal or greater than 8.

6. The system of claim 1, wherein said first time interval is 25 nanoseconds (ns) or shorter.

7. The system of claim 1, wherein said first time interval is 1 ns or shorter.

8. The system of claim 1, wherein said second time interval is between 100 ns to 300 ns.

9. The system of claim 1, wherein said second time interval is of the order of hundreds of microseconds (μ

s).

10. The system of claim 1, wherein said second time interval is of the order of hundreds of milliseconds (ms).