Logic synthesis of multi-level domino asynchronous pipelines
First Claim
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1. A computer-implemented method for optimizing a circuit design, comprising:
- generating a gate level circuit description corresponding to the circuit design, the gate level circuit description comprising a plurality of pipelines across a plurality of levels, the plurality of pipelines including a first pipeline comprising two paths which diverge at a fork stage and converge at a join stage; and
using a linear programming technique, adding a first number of buffers to selected stages of the pipelines such that the pipelines are balanced, at least one performance constraint is satisfied, an objective function characterizing the circuit design is minimized, and each pipeline has at least one gate in each pipeline stage through which it passes, wherein the two paths of the first pipeline include different numbers of cells.
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Abstract
Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
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Citations
27 Claims
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1. A computer-implemented method for optimizing a circuit design, comprising:
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generating a gate level circuit description corresponding to the circuit design, the gate level circuit description comprising a plurality of pipelines across a plurality of levels, the plurality of pipelines including a first pipeline comprising two paths which diverge at a fork stage and converge at a join stage; and using a linear programming technique, adding a first number of buffers to selected stages of the pipelines such that the pipelines are balanced, at least one performance constraint is satisfied, an objective function characterizing the circuit design is minimized, and each pipeline has at least one gate in each pipeline stage through which it passes, wherein the two paths of the first pipeline include different numbers of cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification