Wafer edge surface treatment with liquid meniscus
First Claim
1. An apparatus used in the cleaning of an edge surface of a semiconductor substrate, the apparatus comprising:
- a first portion configured to be disposed over a top edge surface of the semiconductor substrate, the first portion having a plurality of channels defined within the first portion, the plurality of channels extending from a top surface to a bottom surface of the first portion; and
a second portion configured to be disposed under a bottom edge surface of the semiconductor substrate, the second portion having a plurality of channels defined within the second portion, the plurality of channels extending from a top surface to a bottom surface of the second portion, the second portion substantially aligned with the first portion wherein a gap is defined between the top surface of the second portion and the bottom surface of the first portion, the gap enabling the semiconductor substrate to fit therein.
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Accused Products
Abstract
A method for cleaning an edge surface of a semiconductor substrate is disclosed. The proximity head unit is positioned so that the flow head portion and the collection head portion of the proximity head unit are proximate to the edge surface of the semiconductor substrate. The semiconductor substrate is then rotated using one or more powered rollers. During the rotation of the semiconductor substrate, the flow head portion applies a fluid to the edge surface while the collection head portion collects fluid from the edge surface. Additional methods, an apparatuses, and a system for cleaning an edge surface of a semiconductor substrate are also described.
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Citations
8 Claims
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1. An apparatus used in the cleaning of an edge surface of a semiconductor substrate, the apparatus comprising:
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a first portion configured to be disposed over a top edge surface of the semiconductor substrate, the first portion having a plurality of channels defined within the first portion, the plurality of channels extending from a top surface to a bottom surface of the first portion; and a second portion configured to be disposed under a bottom edge surface of the semiconductor substrate, the second portion having a plurality of channels defined within the second portion, the plurality of channels extending from a top surface to a bottom surface of the second portion, the second portion substantially aligned with the first portion wherein a gap is defined between the top surface of the second portion and the bottom surface of the first portion, the gap enabling the semiconductor substrate to fit therein. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification