Method of determining wafer voltage in a plasma reactor from applied bias voltage and current and a pair of constants

• US 7,585,685 B2
• Filed: 08/23/2006
• Issued: 09/08/2009
• Est. Priority Date: 05/16/2003
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Hoffman, Daniel J.
• Primary Examiner(s): Garber; Charles D.
• Assistant Examiner(s): Isaac; Stanetta D
• Application Number:
  US11/508,374
• Publication Number:
  US 20060278609A1
• Time in Patent Office: 1,112 Days
• Field of Search: 438/10, 438/14, 438/15, 438/706, 438/710, 438/712, 438/715, 438/729, 156/345.24, 156/345.25, 156/345.28, 156/345.43, 156/345.44, 156/345.47, 216/59, 216/61, 216/67, 118/697, 118/712, 118/715, 315/11.21, 257/E21.252
• US Class Current: 438/14
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32935 Monitoring and controlling tubes by information coming from the object and/or discharge

Abstract

The voltage of a wafer on the pedestal of an RF plasma reactor is instantly determined from the applied bias current and the applied bias voltage sampled during plasma processing of the wafer using a pair constants. Prior to plasma processing of the wafer, a determination is made of first and second constants based upon electrical characteristics of a transmission line through which RF power is coupled to the pedestal. During plasma processing of the wafer, the wafer voltage is determined by performing the steps of sampling an RF input current and an RF input voltage at the impedance match circuit; multiplying the RF input voltage by the first constant to produce a first product; multiplying the RF input current by the second constant to produce a second product; and computing a sum of the first and second products.

Claims

1. In a plasma reactor chamber containing a wafer support pedestal having an electrode and an RF bias power generator coupled through an impedance match circuit to the input end of a transmission line whose output end is coupled to the electrode, a method of measuring plasma ion energy or wafer voltage of a wafer on the pedestal during plasma processing of the wafer, comprising:

prior to plasma processing of the wafer, determining first and second constants characteristic of the plasma reactor chamber and storing said first and second constants in a memory;

during plasma processing of the wafer performing the following steps;

a. sampling an RF input current and an RF input voltage at said impedance match circuit;

b. multiplying said RF input voltage by said first constant to produce a first product;

c. multiplying said RF input current by said second constant to produce a second product; and

d. computing a sum of said first and second products.

2. The method of claim 1 wherein the group of steps comprising a, b, c and d is repeated periodically whereby said method provides a nearly continuous stream of measurement samples of wafer voltage.

3. The method of claim 1 wherein said first and second constants are functions of the design of the reactor.

4. The method of claim 3 wherein said first and second constants comprise different functions of the RF electrical characteristics of the transmission line.

5. The method of claim 4 wherein said RF electrical characteristics of the transmission line comprise complex loss coefficient, characteristic impedance and length.

6. The method of claim 5 wherein said electrode of said wafer support pedestal comprises a conductive grid coupled to the output end of said transmission line, said method further comprising:

multiplying said sum by a factor comprising an impedance at the wafer on the pedestal, Z_wafer, divided by an impedance at the electrode, Z_grid.

7. The method of claim 6 wherein said wafer support pedestal comprises a lower dielectric layer separating said electrode from a base conductor layer and an upper dielectric layer separating said electrode from said wafer, and wherein:

said impedance at the electrode, Z_grid, is computed from electrical characteristics of said lower dielectric layer;

said impedance at the wafer on the pedestal, Z_wafer, is computed from electrical characteristics of said upper dielectric layer.

8. In a plasma reactor chamber containing a wafer support pedestal having an internal electrode and an RF bias power generator coupled through an impedance match circuit to the input end of a transmission line whose output end is coupled to the electrode at a junction, a method of measuring plasma ion energy or wafer voltage of a wafer on the pedestal during plasma processing of the wafer, comprising:

prior to plasma processing of the wafer, determining first and second constants characteristic of the plasma reactor chamber and storing said first and second constants in a memory;

during plasma processing of the wafer performing the following steps;

a. sampling an RF input current and an RF input voltage at said impedance match circuit;

b. multiplying said RF input voltage by said first constant to produce a first product;

c. multiplying said RF input current by said second constant to produce a second product; and

d. transforming said RF input current and said RF input voltage at said input end of said transmission line to an electrical quantity at the output end of said transmission line by computing a sum of said first and second products.

9. The method of claim 8 wherein the group of steps comprising a, b, c and d is repeated periodically whereby said method provides a nearly continuous stream of measurement samples of wafer voltage.

10. The method of claim 8 wherein said first and second constants are functions of physical characteristics of the reactor.

11. The method of claim 10 wherein said first and second constants comprise different functions of the RF electrical characteristics of the transmission line.

12. The method of claim 11 wherein said RF electrical characteristics of the transmission line comprise complex loss coefficient, characteristic impedance and length.

13. The method of claim 12 wherein said wafer support pedestal comprises a lower dielectric layer separating said electrode from a base conductor layer and an upper dielectric layer separating said electrode from said wafer, said method further comprising:

transforming said electrical quantity at said junction across said upper dielectric layer by multiplying said sum by a factor comprising an impedance at the wafer on the pedestal, Z_wafer, divided by an impedance at the electrode, Z_grid.

14. The method of claim 13 wherein:

said impedance at the electrode, Z_grid, is computed from electrical characteristics of said lower dielectric layer;

said impedance at the wafer on the pedestal, Z_wafer, is computed from electrical characteristics of said upper dielectric layer.