High-k/metal gate MOSFET with reduced parasitic capacitance

• US 7,585,716 B2
• Filed: 06/27/2007
• Issued: 09/08/2009
• Est. Priority Date: 06/27/2007
• Status: Expired due to Fees

• Current Assignee: Tessera, Inc. (Adeia, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo
• Primary Examiner(s): Vu; David
• Assistant Examiner(s): FOX, BRANDON C
• Application Number:
  US11/769,150
• Publication Number:
  US 20090001480A1
• Time in Patent Office: 804 Days
• Field of Search: 257/E21.453, 257/900, 257/386, 438/900, 438/183
• US Class Current: 438/183
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal-containing gate conductor 30 has gate corners 31 located at a base segment of the metal-containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30. The gate spacer 36 is located upon an upper surface of both the gate dielectric 18 and the high-k gate dielectric that is present at the gate corners 31.

Claims

1. A method of forming a semiconductor structure comprising:

providing a structure including a sacrificial gate and a gate dielectric located on a semiconductor substrate, said structure further including an interlevel dielectric located on said semiconductor substrate and separated from said sacrificial gate by a sacrificial spacer;

removing the sacrificial gate and a portion of the gate dielectric that is not protected by the sacrificial spacer to form an opening that exposes a surface of the semiconductor substrate;

forming a U-shaped high-k gate dielectric and a metal-containing gate conductor inside the opening;

removing the sacrificial spacer to expose a portion of the U-shaped high-k gate dielectric that laterally abuts sidewalls of the metal-containing gate conductor;

removing substantially all of the exposed portion of the high-k gate dielectric that laterally abuts the sidewalls of the metal-containing gate conductor from the gate sidewalls; and

forming a gate spacer in an area that previously included the sacrificial spacer and a portion of the U-shaped high-k gate dielectric to provide at least one MOSFET comprising a gate stack including, from bottom to top, the high-k gate dielectric and the metal-containing gate conductor, said metal-containing gate conductor having gate corners located at a base segment of the metal-containing gate conductor, wherein said metal-containing gate conductor has vertical sidewalls devoid of said high-k gate dielectric except at said gate corners, and wherein the gate dielectric is laterally abutting said high-k gate dielectric which is present at said gate corners and said gate spacer is laterally abutting said metal-containing gate conductor and is located upon an upper surface of both the gate dielectric and the high-k gate dielectric that is present at the gate corners.

2. The method of claim 1 further comprising forming an interlevel dielectric material having conductively filled contact vias that extend to the surface of the semiconductor substrate which includes source and drain regions of the at least one MOSFET.

3. The method of claim 2 further comprising forming a spacer liner between the gate spacer and the interlevel dielectric material, the metal-containing gate conductor and the upper surface of both the gate dielectric and the high-k gate dielectric that is present at gate corners of said metal-containing gate conductor.

4. The method of claim 2 further comprising strengthening a portion of said high-k gate dielectric located at gate corners of said metal-containing gate conductor to increase bonding therein as compared to said high-k gate dielectric that is located directly beneath said metal-containing gate conductor.

5. The method of claim 4 wherein said strengthening is obtained by ion implantation one of oxygen ions and nitrogen ions or by a thermal process.

6. The method of claim 2 wherein said forming said gate spacer includes forming a void within in an interior region of said gate spacer.