Dual stress liner device and method

• US 7,585,720 B2
• Filed: 07/05/2006
• Issued: 09/08/2009
• Est. Priority Date: 07/05/2006
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Inventors: Sudo, Gaku
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US11/428,692
• Publication Number:
  US 20080050869A1
• Time in Patent Office: 1,161 Days
• Field of Search: 438/197, 438/199, 438/228, 438/233, 438/279, 438/305, 257/E21.002, 257/211, 257/214, 257/336, 257/414, 257/576, 257/583, 257/597
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

depositing a first stress liner on a silicon layer;

depositing a second stress liner on the silicon layer, wherein a portion of said second stress liner overlaps a portion of said first stress liner above a top of an interconnect structure;

polishing said second stress liner to remove only said portion of said second stress liner overlapping said portion of said first stress liner above the top of the interconnect structure, wherein said polishing uses said first stress liner and a portion of the second stress liner as a stopper, and wherein said polishing leaves the first stress liner above the interconnect structure; and

forming first and second conductive contacts through said first and second stress liners, respectively.

2. The method of claim 1, further comprising the step of embedding an oxide layer in the silicon layer under said conductive interconnect structure.

3. The method of claim 1, further comprising the step of forming a third contact through the first and second stress liners to electrically contact said conductive interconnect structure.

4. The method of claim 1, further comprising the step of depositing an insulating film over said first and second stress liners before said step of polishing.

5. The method of claim 4, further comprising the step of depositing a second insulating film over said first insulating film after said step of polishing and before said step of forming said first and second contacts.

6. The method of claim 1, wherein said first stress liner is a tensile stress liner and said second stress liner is a compressive stress liner.

7. The method of claim 6, wherein said stress liners are SiN stress liners.

13. The method of claim 1, wherein said first stress liner applies a first type of stress on the silicon layer, and said second stress liner applies a second type of stress, opposite the first type of stress, on the silicon layer.

14. The method of claim 1, wherein the first stress liner used as a stopper lies over a second interconnect structure, and the portion of the second stress liner used as a stopper lies over a third interconnect structure.

17. The method of claim 14, wherein said polishing leaves the first stress liner over the second interconnect structure and leaves the second stress liner over the third interconnect structure.

18. The method of claim 14, wherein

said depositing a first stress liner deposits the first stress liner to continuously extend above the second interconnect structure, above the silicon layer, and above the interconnect structure, and

said depositing a second stress liner deposits the second stress liner to continuously extend above the third interconnect structure, above the silicon layer, and above the portion of the first stress liner above the interconnect structure.

8. A method of manufacturing a semiconductor device, comprising the steps of:

forming first and second pluralities of transistor wells on a semiconductor substrate;

depositing a first stress liner contacting said first plurality of said wells;

depositing a second stress liner contacting said second plurality of said wells, wherein a portion of said second stress liner overlaps a portion of said first stress liner above a top of an interconnect structure;

depositing a first insulating film on said stress liners;

polishing said first insulating film and said second stress liner to remove only said portion of said second stress liner overlapping said portion of said first stress liner above the top of the interconnect structure, wherein said polishing uses said first stress liner and a portion of the second stress liner as a stopper, and wherein said polishing leaves the first stress liner above the interconnect structure;

depositing a second insulating film on said first insulating film after said polishing;

forming first and second contacts through said first and second stress liners, respectively.

9. The method of claim 8, wherein said step of forming first and second contacts further comprises the step of forming a trench through both of said insulating films and only one of said stress liners to reach first and second ones of said wells, respectively.

10. The method of claim 8, further comprising the step of forming a third contact through at least said second insulating film to reach a gate structure on said device, wherein said contact contacts said first stress liner on a first side, and said second stress liner on a second side.

11. The method of claim 10, wherein said contact directly contacts said first and second stress liners.

12. The method of claim 10, wherein said gate structure separates said semiconductor into n-type and p-type device regions.

15. The method of claim 8, wherein one of said stress liners is a tensile stress liner, and the other of said stress liners is a compression stress liner.

16. The method of claim 8, wherein the first stress liner used as a stopper lies over a second interconnect structure, and the portion of the second stress liner used as a stopper lies over a third interconnect structure.

19. The method of claim 16, wherein said polishing leaves the first stress liner over the second interconnect structure and leaves the second stress liner over the third interconnect structure.

20. The method of claim 16, wherein

said depositing a first stress liner deposits the first stress liner to continuously extend above the second interconnect structure, above the silicon layer, and above the interconnect structure, and

said depositing a second stress liner deposits the second stress liner to continuously extend above the third interconnect structure, above the silicon layer, and above the portion of the first stress liner above the interconnect structure.