×

Dual stress liner device and method

  • US 7,585,720 B2
  • Filed: 07/05/2006
  • Issued: 09/08/2009
  • Est. Priority Date: 07/05/2006
  • Status: Expired due to Fees
First Claim
Patent Images

1. A method of manufacturing a semiconductor device, comprising the steps of:

  • depositing a first stress liner on a silicon layer;

    depositing a second stress liner on the silicon layer, wherein a portion of said second stress liner overlaps a portion of said first stress liner above a top of an interconnect structure;

    polishing said second stress liner to remove only said portion of said second stress liner overlapping said portion of said first stress liner above the top of the interconnect structure, wherein said polishing uses said first stress liner and a portion of the second stress liner as a stopper, and wherein said polishing leaves the first stress liner above the interconnect structure; and

    forming first and second conductive contacts through said first and second stress liners, respectively.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×