Insulated gate type semiconductor device and method for fabricating the same

• US 7,585,732 B2
• Filed: 02/26/2008
• Issued: 09/08/2009
• Est. Priority Date: 02/19/2001
• Status: Active Grant

• Current Assignee: Renesas Semiconductor Package & Test Solutions Co., Ltd. (Renesas Electronics Corporation)
• Original Assignee: Hitachi TOBU Semiconductor Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Oishi, Kentaro, Inagawa, Hiroshi, Machida, Nobuo
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US12/037,139
• Publication Number:
  US 20080153235A1
• Time in Patent Office: 560 Days
• Field of Search: 438/135, 438/138, 438/270, 257/E21.384
• US Class Current: 438/270
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Claims

1. A method of manufacturing a semiconductor device including a trench-gate type MISFET, comprising the steps of:

(a) providing a semiconductor substrate having a first semiconductor layer on a front surface thereof, the first semiconductor layer having a major surface, the semiconductor substrate having a back surface opposite to the front surface, and the semiconductor substrate and semiconductor layer having a first conduction type;

(b) forming a first insulating film over the major surface of the first semiconductor layer;

(c) forming trenches in the first insulating film and the first semiconductor layer;

(d) forming a gate insulating film of the MISFET on an inner wall of each trench;

(e) forming a conductive film over the first insulating film and on each gate insulating film;

(f) etching the conductive film selectively to form a gate conductive layer of the MISFET on each gate insulating film;

(g) after the step (f), removing the first insulating film over the major surface of the first semiconductor layer so that a top surface of each gate conductive layer is protruded from the major surface of the first semiconductor layer;

(h) forming a base region of the MISFET in each area between adjacent trenches, the base region having a second conduction type opposite to the first conduction type;

(i) forming a source region of the MISFET having the first conduction type on each base region;

(j) forming a second insulating film over the gate conductive layers and the major surface of the first semiconductor layer;

(k) etching the second insulating film selectively to form side wall spacers on side surfaces of each gate conductive layer, the side surfaces being protruded from the major surface of the first semiconductor layer;

(l) after the step (k), etching each area of the major surface of the first semiconductor layer between adjacent trenches to form a respective contact hole, with a corresponding base region and a side surface of a corresponding source region being exposed from the contact hole;

(m) after the step (l), etching each of the side wall spacers selectively so that a top surface of each source region is exposed;

(n) after the step (m), forming a source conductive layer in each contact hole, the source conductive layer being electrically connected to the corresponding source region and the corresponding base region, and the source conductive layer being contacted with the top and side surfaces of each of the source regions; and

(o) forming a drain electrode on the back surface of the semiconductor substrate, the drain electrode being electrically connected to the semiconductor substrate and first semiconductor layer.

2. A method of manufacturing a semiconductor device according to claim 1, wherein in the step (l), the contact hole is formed in a self-alignment manner using the side wall spacers of adjacent gate conductive layers.

3. A method of manufacturing a semiconductor device according to claim 1, further comprising the step of:

(p) after the step (l), forming, through the respective contact hole, a contact layer in the corresponding base region, the contact layer having the second conduction type.

4. A method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor layer is an epitaxial layer.

5. A method of manufacturing a semiconductor device according to claim 1, wherein the gate conductive layers are comprised of polycrystalline film.

6. A method of manufacturing a semiconductor device according to claim 1, wherein the side wall spacers are comprised of silicon oxide film.

7. A method of manufacturing a semiconductor device according to claim 1, wherein, in the step (n), a gate electrode is formed, and the gate electrode is electrically connected to the gate conductive layers.

8. A method of manufacturing a semiconductor device according to claim 7,

wherein the source conductive layer and the gate electrode are comprised of aluminum film.