Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby

• US 7,585,734 B2
• Filed: 03/05/2008
• Issued: 09/08/2009
• Est. Priority Date: 06/29/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ahn, Jong-hyon, Kang, Tae-Woong
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Nicely; Joseph C
• Application Number:
  US12/074,580
• Publication Number:
  US 20080160684A1
• Time in Patent Office: 552 Days
• Field of Search: 438156-157, 438/164, 438/184, 438/197, 438230-232, 438/303, 438365-366, 438/595, 438/696, 438/283, 438/301, 438305-306, 438/514, 438/527, 438/288, 438/149, 438/151, 257/328, 257/369, 257/347, 257/408, 257/412, 257/623, 257/E21.618, 257/E21.619, 257/E21.621, 257/E21.623, 257/E21.626, 257E21633- 21635, 257/E21.64, 257/E21.637, 257/E29.028
• US Class Current: 438/283
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, in which an active pattern is formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, a gate insulating layer is formed on the channel regions, and a patterned gate electrode is formed on the gate insulating layer while maintaining a shape conformal to the active pattern.

Claims

1. A method of fabricating a multi-gate transistor comprising:

forming an active pattern on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed;

forming a gate insulating layer on the channel regions;

forming a conductive layer for a gate electrode on the gate insulating layer conformally to the active pattern;

forming a sacrificial layer for planarizing an upper surface of the substrate by filling a step of the conformally formed conductive layer for the gate electrode;

forming the gate electrode by patterning the conductive layer and the sacrificial layer;

forming a first spacer on the gate electrode and the lateral surfaces of the sacrificial layer remaining on the gate electrode; and

removing the remaining sacrificial layer after forming the gate electrode,

wherein in the removing of the sacrificial layer, the first spacer formed on the lateral surface of the sacrificial layer is removed together with the sacrificial layer so that the first spacer remains on the lateral surfaces of the gate electrode.

2. The method of claim 1, wherein forming the sacrificial layer comprises:

forming the sacrificial layer on the surface of the resulting structure having the conductive layer; and

filling the step of the conformally formed conductive layer by planarizing the sacrificial layer.

3. The method of claim 2, wherein the sacrificial layer is an amorphous silicon layer.

4. The method of claim 2, wherein planarizing the sacrificial layer includes using a chemical mechanical polishing (CMP) process.

5. The method of claim 4, after forming of the conductive layer, further comprising forming a polishing stop layer on the conductive layer.

6. The method of claim 5, wherein the polishing stop layer is formed of a material selected from the group consisting of SiO₂, SiN, SiON, and a combination thereof.

7. The method of claim 1, before the patterning of the conductive layer and the sacrificial layer, further comprising:

forming an insulating layer on the substrate;

forming a hard mask by patterning the insulating layer using a pattern for defining the gate electrode; and

forming the gate electrode by etching the conductive layer and the sacrificial layer using the hard mask as an etch mask.

8. The method of claim 1, wherein the remaining sacrificial layer is removed by a selective wet etching process.

9. The method of claim 8, wherein one of a tetramethylammonium hydroxide (TMAH) solution and a mixed solution of nitric acid, HF and water is used during the selective wet etching process.

10. The method of claim 1, wherein the first spacer is formed at a temperature of 550 degrees C. or less.

11. The method of claim 10, wherein the first spacer is formed of a material selected from the group consisting of SiO₂, SiN, SiON, and a combination thereof.

12. The method of claim 1, after removing the sacrificial layer, further comprising:

performing shallow low-concentration ion implantation by implanting ions into the active pattern using the gate electrode and the first spacer as ion-implantation masks;

forming a second spacer on the lateral surfaces of the first spacer; and

performing deep high-concentration ion implantation by implanting ions into the active pattern using the first and second spacers and the gate electrode as ion-implantation masks.

13. The method of claim 1, wherein forming the active pattern comprises:

preparing a silicon-on-insulator (SOI) wafer; and

forming the active pattern by patterning a silicon layer of the SOI wafer.

14. The method of claim 1, wherein forming the active pattern includes forming a plurality of active patterns on the substrate, the active patterns having two or more surfaces on which the channel regions are to be formed.