Single chip with multi-LED

• US 7,586,129 B2
• Filed: 12/01/2006
• Issued: 09/08/2009
• Est. Priority Date: 12/14/2005
• Status: Active Grant

• Current Assignee: Advanced Optoelectronic Technology, Inc.
• Original Assignee: Advanced Optoelectronic Technology, Inc.
• Inventors: Kuo, Chester, Ma, Chih Pang, Hsu, Chih Peng
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Patton, Paul E
• Application Number:
  US11/606,937
• Publication Number:
  US 20070131958A1
• Time in Patent Office: 1,012 Days
• Field of Search: None
• US Class Current: 257/99
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/385 the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A single chip with multi-LED comprises a substrate on which an N-type semiconductor layer, an active layer and a P-type semiconductor layer are successively stacked. At least one N-type electrode is connected to the N-type semiconductor layer, and is exposed to an opening through the active layer and the P-type semiconductor layer. Further, at least one groove divides the P-type semiconductor layer into a plurality of separated regions, and a P-type electrode is disposed on each separated region.

Claims

1. A single chip with multi-LED, comprising:

a substrate;

an N-type semiconductor layer disposed on the substrate;

an active layer disposed on a part of the N-type semiconductor layer;

a P-type semiconductor layer disposed on the active layer;

a plurality of grooves dividing the P-type semiconductor layer and the active layer into a plurality of separated regions;

a plurality of P-type electrodes respectively disposed in the separated regions of the P-type semiconductor layer; and

an N-type electrode disposed on the N-type semiconductor layer;

wherein the P-type electrodes and the N-type electrode are on a same side of the N-type semiconductor layer and the P-type electrodes are connected to the N-type electrode in parallel.

2. The single chip with multi-LED of claim 1, wherein the N-type semiconductor layer is exposed in the grooves, and the N-type electrode is located on the N-type semiconductor layer in the grooves.

3. The single chip with multi-LED of claim 1, wherein the P-type semiconductor layer and the active layer are divided into four separated regions, and the N-type electrode is located in the center of the four regions.

4. The single chip with multi-LED of claim 3, wherein the area of one of the N-type electrode and the P-type electrodes is suitable to accommodate two probes to contact simultaneously.

5. The single chip with multi-LED of claim 1, wherein the P-type semiconductor layer and the active layer are divided into two separated regions, and the N-type electrode is located between the two regions.

6. The single chip with multi-LED of claim 1, wherein the P-type electrodes and the N-type electrode are disposed in a manner that the distance between the N-type electrode and each of the P-type electrodes is maximum and the P-type electrodes have a equal distance between each other.

7. The single chip with multi-LED of claim 1, further comprising a transparent conductive layer (TCL) disposed on the separated P-type semiconductor layer respectively, wherein the TCL has at least one slot between the N-type electrode and the P-type electrodes.

8. The single chip with multi-LED of claim 1, wherein the grooves divides the N-type semiconductor layer into a plurality of separated regions.

9. A single chip with multi-LED, comprising:

a substrate;

an N-type semiconductor layer disposed on the substrate;

an active layer disposed on a part of the N-type semiconductor layer;

a P-type semiconductor layer disposed on the active layer;

at least one groove dividing the P-type semiconductor layer and the active layer into a plurality of separated regions and not dividing the N-type semiconductor layer into a plurality of separated regions;

a plurality of P-type electrodes respectively disposed in the separated regions of the P-type semiconductor layer; and

an N-type electrode disposed on the N-type semiconductor layer and not overlapping the P-type electrodes.

10. The single chip with multi-LED of claim 9 wherein the N-type semiconductor layer is exposed in the groove, and the N-type electrode is located on the N-type semiconductor layer in the groove.

11. The single chip with multi-LED of claim 9 wherein the P-type semiconductor layer and the active layer are divided into four separated regions, and the N-type electrode is located in the center of the four regions.

12. The single chip with multi-LED of claim 11, wherein the area of one of the N-type electrode and the P-type electrode is suitable to accommodate contacting with two probes simultaneously.

13. The single chip with multi-LED of claim 9, wherein the P-type semiconductor layer and the active layer are divided into two separated regions, and the N-type electrode is located between the two regions.

14. A single chip with multi-LED, comprising:

a substrate;

an N-type semiconductor layer disposed on the substrate;

an active layer disposed on a part of the N-type semiconductor layer;

a P-type semiconductor layer disposed on the active layer;

at least one groove dividing the P-type semiconductor layer and the active layer into a plurality of separated regions;

a plurality of P-type electrodes respectively disposed in the separated regions of the P-type semiconductor layer; and

at least one N-type electrode disposed on the N-type semiconductor layer;

wherein the at least one N-type electrode and the P-type electrodes are connected in parallel, or antiparallel.