Photo-sensor and pixel array with backside illumination and method of forming the photo-sensor

• US 7,586,139 B2
• Filed: 02/17/2006
• Issued: 09/08/2009
• Est. Priority Date: 02/17/2006
• Status: Active Grant

• Current Assignee: Smartsens Technology (Cayman) Co., Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Loiseau, Alan, Gambino, Jeffrey P., Rassel, Richard J., Jaffe, Mark D., Adkisson, James W.
• Primary Examiner(s): Doan; Theresa T
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US11/276,218
• Publication Number:
  US 20070194397A1
  US 20060102973A1 (withdrawn)
• Time in Patent Office: 1,299 Days
• Field of Search: 257/447, 257/460, 257/440, 257/431, 257/432, 257/228, 257/225, 257290-292, 257/294, 257/E31.055, 257/E31.097
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.

Claims

1. An imaging sensor comprising:

a pixel array, each pixel comprising;

a semiconductor island of a first conduction type,

a dielectric layer;

an isolation well of a second conduction type in one surface of said semiconductor layer, said second conduction type being opposite said first conduction with said isolation well forming a photo-sensor on said one surface with said semiconductor layer, the other surface of said semiconductor island being at and adjacent to said dielectric layer,

cell wiring to said cell extending from photo-sensor structures in said one surface, and

a color filter separated from said semiconductor layer by said dielectric layer;

a trench to said dielectric layer surrounding each said semiconductor island; and

a protective layer on said pixel array at pixel color filters, an optical signal passing through said protective layer, through said dielectric layer and then, through said semiconductor island to said photo-sensor, being filtered by said color filters and causing current flow across said semiconductor island and said isolation well junction selectively sensed by a corresponding said photo-sensor.

2. An imaging sensor as in claim 1, wherein said semiconductor island is 2-6 μ

m thick silicon island separated from adjacent silicon islands by said trench and said color filter is 0.5-1.5 μ

m thick and said dielectric layer a 0.1-1.0 μ

m thick oxide layer.

3. An imaging sensor as in claim 2, wherein said silicon island is doped N-type, said isolation well is a P-well in said N-type silicon island forming a photodiode and NFETs on said P-well are connected to said photodiode to selectively sense said optical signal.

4. An imaging sensor as in claim 3, wherein said active silicon layer and said oxide layer are silicon on insulator (SOI) layers in a CMOS SOI chip and said NFETs comprise:

a first NFET connected between the cathode of said photodiode and a supply voltage (V_dd), said first NFET being gated by a reset signal;

a second NFET connected at the drain to said supply voltage and gated by said cathode; and

a third NFET connected between the source of said second NFET and a data output, said third NFET being gated by a pixel select signal.

5. An imaging sensor as in claim 2, wherein a handle layer bonded to a surface above said cell wiring, said pixel array being sandwiched between said protective layer and said handle layer.

6. An imaging sensor cell comprising:

a semiconductor layer of a first conduction type;

a dielectric layer;

an isolation trench to said dielectric layer surrounding said semiconductor layer;

an isolation well of a second conduction type in one surface of said semiconductor layer, said second conduction type being opposite said first conduction type with said isolation well forming a photo-sensor on said one surface with said semiconductor layer, the other surface of said semiconductor layer being at and adjacent to said dielectric layer;

a color filter separated from said semiconductor layer by said dielectric layer; and

a protective layer on said color filter, light passing through said protective layer, through said dielectric layer and then, through said semiconductor layer, and filtered by said color filter causing current flow across said semiconductor layer and said isolation well junction being selectively sensed by said photo-sensor.

7. An imaging sensor cell as in claim 6, wherein wiring to said cell extends away from said semiconductor layer from photo-sensor structures in said one surface.

8. An imaging sensor cell as in claim 6, wherein said semiconductor layer is an active silicon layer and said dielectric layer is an oxide layer.

9. An imaging sensor cell as in claim 8, wherein said active silicon layer is 2-6 μ

m thick and said oxide layer is 0.1-1.0 μ

m.

10. An imaging sensor cell as in claim 8, wherein said active silicon layer is doped with an N-type dopant and said isolation well is a P-well in said N-type active silicon layer forming a photodiode, said imaging sensor cell further comprising a plurality of NFETs formed in said P-well, said NFETs connected to selectively sense an optical signal to said photodiode.

11. An imaging sensor cell as in claim 10, wherein said plurality of NFETs comprises:

a first NFET connected between the cathode of said photodiode and a supply voltage (V_dd), said first NFET being gated by a reset signal;

a second NFET connected at the drain to said supply voltage and gated by said cathode; and

a third NFET connected between the source of said second NFET and a data output, said third NFET being gated by a pixel select signal.

12. An imaging sensor cell as in claim 6, wherein said color filter is in a layer of color filters, said protective layer on said layer of color filters, light passing through said protective layer being filtered by color filters in said layer of color filters.

13. An imaging sensor cell as in claim 12, wherein said protective layer is a quartz layer.

14. An imaging sensor cell as in claim 12, wherein said protective layer further filters out invisible light.

15. An imaging sensor cell comprising:

a silicon layer;

a photodiode in a first surface of said silicon layer, said photodiode comprising the junction of an isolation well in said silicon layer;

a dielectric layer on the other surface of said silicon layer;

a photo-sensor on said isolation well and including said photodiode;

a color filter separated from said silicon layer by said dielectric layer; and

a protective layer on said color filter, light passing through said protective layer, said dielectric layer and said silicon layer filtered color filter photodiode junction current being selectively sensed by said photo-sensor.

16. A CMOS chip including an imaging sensor cell as in claim 15, wherein said dielectric layer is an oxide layer and wiring to said cell extends away from said silicon layer from photo-sensor structures in said one surface.

17. A CMOS chip as in claim 16, wherein said active silicon layer is doped with an N-type dopant and said isolation well is a P-well in said N-type active silicon layer forming said photodiode, said imaging sensor cell further comprising a plurality of NFETs formed in said P-well, said NFETs connected to selectively sense an optical signal to said photodiode.

18. A CMOS chip as in claim 17, wherein said plurality of NFETs comprises:

a first NFET connected between the cathode of said photodiode and a supply voltage (V_dd), said first NFET being gated by a reset signal;

a second NFET connected at the drain to said supply voltage and gated by said cathode; and

a third NFET connected between the source of said second NFET and a data output, said third NFET being gated by a pixel select signal.

19. A CMOS chip as in claim 18, wherein said color filter is in a layer of color filters, said protective layer on said layer of color filters, light passing through said protective layer being filtered by color filters in said layer of color filters.

20. An imaging sensor cell comprising:

a semiconductor layer of a first conduction type;

a dielectric layer, wherein said semiconductor layer is an active silicon layer and said dielectric layer is an oxide layer;

an isolation trench to said dielectric layer surrounding said semiconductor layer;

an isolation well of a second conduction type in one surface of said semiconductor layer, said second conduction type being opposite said first conduction type with said isolation well forming a photo-sensor on said one surface with said semiconductor layer, the other surface of said semiconductor layer being at and adjacent to said dielectric layer, wherein said active silicon layer is doped with an N-type dopant and said isolation well is a P-well in said N-type active silicon layer forming a photodiode, said imaging sensor cell further comprising a plurality of NFETs formed in said P-well, said NFETs connected to selectively sense an optical signal to said photodiode, wherein said plurality of NFETs comprises;

a first NFET connected between the cathode of said photodiode and a supply voltage (V_dd), said first NFET being gated by a reset signal,

a second NFET connected at the drain to said supply voltage and gated by said cathode, and

a third NFET connected between the source of said second NFET and a data output, said third NFET being gated by a pixel select signal, wherein said active silicon layer and said oxide layer are silicon on insulator (SOI) layers in a CMOS SOI chip;

a color filter separated from said semiconductor layer by said dielectric layer; and

a protective layer on said color filter, light passing through said protective layer, through said dielectric layer and then, through said semiconductor layer, and filtered by said color filter causing current flow across said semiconductor layer and said isolation well junction being selectively sensed by said photo-sensor.