Power semiconductor device having a voltage sustaining region that includes doped columns formed by terraced trenches

• US 7,586,148 B2
• Filed: 07/31/2006
• Issued: 09/08/2009
• Est. Priority Date: 03/21/2002
• Status: Expired due to Fees

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): Mai; Anh D
• Application Number:
  US11/496,233
• Publication Number:
  US 20060267083A1
• Time in Patent Office: 1,135 Days
• Field of Search: 257/328, 257/E21.418, 257/E29.257, 257/339, 257/342, 257/E26.418, 438/212, 438/268
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, an epitaxial layer is deposited on the substrate. The epitaxial layer has a first or a second conductivity type. Next, at least one terraced trench is formed in the epitaxial layer. The terraced trench has a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls and bottom of the trench. A dopant of a conductivity type opposite to the conductivity type of the epitaxial layer is implanted through the barrier material lining the annular ledge and at the trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region. The dopant is diffused in the annular doped region and the another doped region to cause the regions to overlap one another, whereby a continuous doped column is formed in the epitaxial layer. A filler material is deposited in the terraced trench to substantially fill the terraced trench. Finally, at least one region of conductivity type opposite to the conductivity type of the epitaxial layer is formed over the voltage sustaining region to define a junction therebetween.

Claims

1. A power semiconductor device comprising:

a substrate of a first conductivity type;

a voltage sustaining region disposed on said substrate, said voltage sustaining region including;

an epitaxial layer having a first or second conductivity type;

at least one terraced trench located in said epitaxial layer, said terraced trench having a trench bottom and a plurality of terrace portions that differ in width to define a plurality of annular ledges therebetween;

at least one doped column having a dopant of a conductivity type opposite to the conductivity type of the epitaxial layer, said doped column being formed from at least one annular doped region and another doped region diffused into one another, said at least one annular doped region and said another doped region being located in said epitaxial layer adjacent to and below said plurality of annular ledges and said trench bottom, respectively, wherein the trench bottom and the plurality of terrace portions each have a same total charge;

a filler material substantially filling said terraced trench; and

at least one active region of a conductivity opposite to the conductivity type of the epitaxial layer disposed over said voltage sustaining region to define a junction therebetween,

wherein said epitaxial layer has a given thickness and wherein said plurality of annular ledges are separated by a space substantially equal to 1/(x+1) of said given thickness, where x is equal to or greater than a number of said plurality of annular ledges formed in the voltage sustaining region.

2. The device of claim 1 wherein said filler material is silicon dioxide.

3. The device of claim 1 wherein said filler material is silicon nitride.

4. A power semiconductor device comprising:

a substrate of a first conductivity type;

a voltage sustaining region disposed on said substrate, said voltage sustaining region including;

an epitaxial layer having a first or second conductivity type;

at least one terraced trench located in said epitaxial layer, said terraced trench having a trench bottom and a plurality of terrace portions that differ in width to define at least one annular ledge therebetween;

at least one doped column having a dopant of a conductivity type opposite to the conductivity type of the epitaxial layer, said doped column being formed from at least one annular doped region and another doped region diffused into one another, said at least one annular doped region and said another doped region being located in said epitaxial layer adjacent to and below said at least one annular ledge and said trench bottom, respectively, wherein the trench bottom and plurality of terrace portions each have a same total charge;

a filler material substantially filling said terraced trench; and

at least one active region of a conductivity opposite to the conductivity type of the epitaxial layer disposed over said voltage sustaining region to define a junction therebetween,

wherein said plurality of portions of the terraced trench includes a smallest width portion and a largest width portion, said smallest width portion being located at a depth in said epitaxial layer such that it is closer to the substrate than a largest width portion,

wherein said plurality of portions of the terraced trench are coaxially located with respect to one another,

wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions, and

wherein a surface area of the at least two annular ledges are substantially equal to one another.

5. The device of claim 4 wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions.

6. The device of claim 4 wherein said material tilling the trench is a dielectric material.

7. The device of claim 4 wherein said dopant is boron.

8. The device of claim 4 wherein said at least one active region further includes:

a gate dielectric and a gate conductor disposed above said gate dielectric;

first and second body regions located in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type; and

first and second source regions of the first conductivity type located in the first and second body regions, respectively.

9. The device of claim 8 wherein said body regions include deep body regions.

10. The device of claim 4 wherein said terraced trench has a circular cross-section.

11. The device of claim 4 wherein said terraced trench has a cross-sectional shape selected from the group consisting of a square, rectangle, octagon, and a hexagon.