Dual port memory trigger system for a ground penetrating radar

• US 7,586,433 B1
• Filed: 03/26/2007
• Issued: 09/08/2009
• Est. Priority Date: 03/26/2007
• Status: Expired due to Fees

• Current Assignee: Mal GeoScience AB
• Original Assignee: Mal GeoScience AB
• Inventors: Johansson, Bernth A. T., Leijon, Tommy
• Primary Examiner(s): Sotomayor; John B
• Application Number:
  US11/691,161
• Time in Patent Office: 897 Days
• Field of Search: 342/22, 342/73, 342 82- 89, 342200-204
• US Class Current: 342/22
• CPC Class Codes: G01S 13/885 for ground probing prospecting or detecting using electromagnetic waves G01V3/12
• CPC Class Codes: G01S 7/295 Means for transforming co-ordinates or for evaluating data, e.g. using computers
• CPC Class Codes: G01V 3/12 operating with electromagnetic waves operating with millimetre waves G01V8/005
• CPC Class Codes: G01V 3/15 specially adapted for use during transport, e.g. by a person, vehicle or boat

Abstract

Systems and methods for generating trigger signals in a ground penetrating radar. In one embodiment, sequence data is generated based on a desired triggering sequence for an array of antennas. The sequence may be generated based on position data from position devices and operational modes. According to one embodiment, as the sequence data is generated it is transferred to, and stored on, a dual port memory device through a first side of the dual port memory device. The sequence data can then be accessed independently through a second side of the dual port memory device. This data may be used by a logical network to produce antenna trigger signals as a logical combination of timing input signals and the sequence data.

Claims

1. A system for triggering an array of antennas in a radar system, including:

memory to store and output multiple-bit binary sequence data representative of a desired triggering sequence for the array of antennas;

a logical network to receive a timing input signal and the sequence data from the memory, to produce a plurality of trigger signals as a logical function of the timing input signal and the sequence data; and

wherein the memory includes dual port memory comprising a first data port for receiving the multiple-bit sequence data and a second data port for outputting the multiple-bit sequence data to the logical network.

2. The system of claim 1 wherein:

the memory stores and outputs transmit antenna sequence data representative of a desired triggering sequence for an array of transmit antennas; and

the logical network receives a transmit timing input signal and produces a plurality of transmit antenna trigger signals as a logical function of the transmit timing input signals and the transmit antenna sequence data.

3. The system of claim 1 wherein:

the memory stores and outputs receive antenna sequence data representative of a desired triggering sequence for an array of receive antennas; and

the logical network receives a receive timing input signal and produces a plurality of receive antenna trigger signals as a logical function of the receive timing input signals and the receive antenna sequence data.

4. The system of claim 1 wherein the dual port memory further includes:

a first address port for receiving addresses for storing the multiple-bit sequence data; and

a second address port for receiving a counter signal for causing the multiple-bit sequence data to be outputted at the second data port.

5. The system of claim 4 and further including a counter for providing the counter signal to the second address port of the dual port memory.

6. The system of claim 4 and further including an array central processing unit for providing the sequence data to the first data port of the dual port memory.

7. The system of claim 6, further comprising at least one data receiver coupled to the array central processing unit by a synchronization line, wherein the data receiver includes:

a conversion module to receive serial data from an antenna receiver and output the received serial data as parallel data;

a data receiver dual port memory having a first side and a second side attached to the master bus, wherein the first side and the second side of the data receiver dual port memory independently provide access to data locations within the data receiver dual port memory; and

a receiver computer communicably coupled to the conversion module, wherein the receiver computer is capable of receiving the parallel data output from the conversion module and transfer requested data to the first side of the data receiver dual port memory for storage.

8. The ground penetrating radar antenna array control unit of claim 7, wherein the receiver computer determines how to collect data based a subset of received measurement parameters.

9. The system of claim 1 wherein the multiple-bit sequence data was generated by a processing unit based on position information received from one or more positioning devices and current operational modes.

10. The system of claim 1 wherein the logical network includes AND gates for producing the trigger signals as a logical AND function of the timing input signal and the bits of the sequence data.

11. A trigger generation system for a ground penetrating radar having an array of transmit and receive antennas, including:

a transmit dual port memory to store and output multiple-bit transmit antenna sequence data, including;

a first data port for receiving the transmit antenna sequence data;

a first address port for receiving transmit storage addresses for the transmit antenna sequence data;

a second data port for outputting the transmit antenna sequence data; and

a second address port for receiving a counter signal and causing the transmit antenna sequence data to be outputted at the first data port;

a transmit counter coupled to the second address port of the transmit dual port memory, for receiving a clock signal and producing the counter signal;

a transmit logical network coupled to the second data port of the transmit dual port memory, for receiving a transmit timing input signal and producing a plurality of transmit trigger signals as a logical function of the transmit timing input signal and the transmit antenna sequence data;

a receive dual port memory to store and output multiple-bit receive antenna sequence data, including;

a first data port for receiving the receive antenna sequence data;

a first address port for receiving receive storage addresses for the receive antenna sequence data;

a second data port for outputting the receive antenna sequence data; and

a second address port for receiving a counter signal and causing the receive antenna sequence data to be outputted at the first data port;

a receive counter coupled to the second address port of the receive dual port memory, for receiving a clock signal and producing the counter signal;

a receive logical network coupled to the second data port of the receive dual port memory, for receiving a receive timing input signal and producing a plurality of receive trigger signals as a logical function of the receive timing input signal and the receive antenna sequence data.

12. The trigger generation system of claim 11 and further including an array processing unit coupled to the transmit dual port memory and the receive dual port memory, for providing the transmit storage addresses and transmit antenna sequence data to the transmit dual port memory, and for providing the receive storage addresses and receive antenna sequence data to the receive dual port memory.

13. The trigger generation system of claim 12 wherein:

the transmit logical network includes combinational logic to generate trigger sequences for transmit antennas based on sequence data received from the transmit dual port memory; and

the receive logical network includes combinational logic to generate trigger sequences for receive antennas based on sequence data received from the receive dual port memory.

14. A method for generating a plurality of trigger signals, the method comprising:

indexing into a memory location within a dual port memory having a first side and a second side allowing independent access to memory locations in the dual port memory;

receiving and storing address and data values through the first side of the dual port memory, wherein the address and data values include a numerical sequence indicating which transmit and receive antennas in an antenna array to activate; and

retrieving the stored address and data values through the second side of the dual port memory.

15. The method of claim 14, further comprising:

receiving positioning information about the antennas in the antenna array; and

determining the numerical sequence indicating which transmit and receive antennas to activate based in part on the received positioning information.

16. The method of claim 14, wherein the receiving and storing address and data values through the first side of the dual port memory occurs substantially at the same time the retrieving the stored address and data values through second side of the dual port memory is occurring.

17. The method of claim 14, further comprising:

communicating the retrieved address and data values to a logical network; and

generating a trigger signal which indicate timing and selection of a subset of antennas to be activated in an antenna array based on a selected operational mode and the communicated address and data values.

18. The method of claim 17, wherein the operation mode chosen from the group consisting of a time base generator mode, a sweep control mode, a transmitter trigger generation mode, and a receiver trigger control mode.

19. The method of claim 17, wherein the logical network includes combinational logic to generate the trigger signals.

20. The method of claim 19, wherein a path within the combination logic from the input each generated trigger output have the same depth.