Apparatus and method for driving liquid crystal display device

• US 7,586,476 B2
• Filed: 08/19/2005
• Issued: 09/08/2009
• Est. Priority Date: 06/15/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Moon, Su Hwan, Chae, Ji Eun, Kwon, Sun Young, Kim, Do Heon
• Primary Examiner(s): Mengistu; Amare
• Assistant Examiner(s): SHARIFI-TAFRESHI, KOOSHA
• Application Number:
  US11/208,417
• Publication Number:
  US 20060284815A1
• Time in Patent Office: 1,481 Days
• Field of Search: 345 94- 96, 345 98-100, 345/103, 345/87, 345/691
• US Class Current: 345/98
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

An apparatus and method for driving a liquid crystal display device are disclosed. The apparatus includes a liquid crystal panel with pixels defined by data and gate lines. A gate driver provides different gate pulses to the odd-column pixels than to the even-column pixels. The gate pulses have different voltages and/or widths. Data drivers provide data voltages having a positive or negative polarity to the data lines. A timing controller controls the gate and data drivers and supplies gate clock pulses that have different voltages and/or widths to the gate driver.

Claims

1. An apparatus for driving a liquid crystal display device, comprising:

a liquid crystal panel comprising an image display including a plurality of data lines, a plurality of gate lines, a plurality of pixels having odd-column pixels each of which is connected to a first side of one of the data lines and connected to an associated odd gate line, and even-column pixels each of which is connected to a second side of one of the data lines and connected to an associated even gate lines;

a gate driver that provides different gate pulses to the odd-column pixels than to the even-column pixels, wherein the gate driver provides gate pulses of different widths to the odd-column pixels and the even-column pixels;

a plurality of data drivers that provide data voltages having a positive or negative polarity to the data lines; and

a timing controller that controls the gate driver and the data driver, wherein the timing controller repeatedly generates first and third gate shift clocks having a first width and a first phase delay for one horizontal period, repeatedly generates second and fourth gate shift clocks having a second width different from the first width and a second phase delay for one horizontal period, and supplies the first to fourth gate shift clocks to the gate driver;

wherein the gate driver comprises a first gate driver circuit that provides gate pulses, which have the first width, to the gate lines connected to the odd-column pixels using the first and the third gate shift clocks; and

a second gate driver circuit that provides gate pulses, which have the second width, to the gate lines connected to the even-column pixels using the second and the fourth gate shift clocks;

wherein the first width of the gate pulses provided to the odd-column pixels is wider than the second width of the gate pulses provided to the even-column pixels; and

wherein the ratio of the first width to the second width is about 10;

7.

2. The apparatus as set forth in claim 1, wherein the gate pulses provided to the odd-column pixels and the even-column pixels overlap each other.

3. The apparatus as set forth in claim 1, wherein the data driver reverses the polarity of the data voltages for every horizontal period.

4. The apparatus as set forth in claim 1, wherein the gate driver is formed on the liquid crystal panel.

5. A method for driving a liquid crystal display device which comprises an image display including a plurality of data lines, a plurality of gate lines, a plurality of pixels having odd-column pixels each of which is connected to a first side of one of the data lines and connected to an associated odd one of the gate lines, and even-column pixels each of which is connected to a second side of one of the data lines and connected to an associated even one of the gate lines, the method comprising:

providing different gate pulses to the odd-column pixels than to the even-column pixels, wherein gate pulses provided to the odd-column pixels have different widths from gate pulses provided to the even-column pixels;

providing data voltages having a positive or negative polarity to each of the data lines in synchronization with the gate pulses;

repeatedly generating first and third gate shift clocks having a first width and a first phase delay for one horizontal period; and

repeatedly generating second and fourth gate shift clocks having a second width different from the first width and a second phase delay for one horizontal period;

wherein supplying the gate pulses having the different widths comprises supplying the gate pulses, which have the first width, to the gate lines connected to the odd-column pixels using the first and the third gate shift clocks; and

supplying the gate pulses, which have the second width, to the gate lines connected to the even-column pixels using the second and the fourth gate shift clocks;

wherein the first width of the gate pulses provided to the odd-column pixels is wider than the second width of the gate pulses provided to the even-column pixels; and

wherein the ratio of the first width to the second width is about 10;

7.

6. The method as set forth in claim 5, wherein the gate pulses of the first width overlap the gate pulses of the second width.

7. The method as set forth in claim 5, wherein the polarity of the data voltage is reversed for every horizontal period.