Method for analyzing overlay errors

• US 7,586,609 B2
• Filed: 04/21/2005
• Issued: 09/08/2009
• Est. Priority Date: 04/21/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Wu, I-Pien, Hsu, Chia-Yu, Chien, Chen-Fu, Lin, Shun-Li
• Primary Examiner(s): Chowdhury; Tarifur R.
• Assistant Examiner(s): Akanbi; Isiaka O
• Application Number:
  US11/112,115
• Publication Number:
  US 20060238761A1
• Time in Patent Office: 1,601 Days
• Field of Search: 356399-401
• US Class Current: 356/401
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

Abstract

A method for analyzing overlay errors in lithography is described. Interfield sampling and intrafield sampling are first conducted to sample multiple positions on each of the wafers, and then the overlay error value at each of the positions is measured. An overlay error model including coefficients of intrafield and interfield overlay errors of different types is used to fit the measured overlay error values with respect to the sampled positions. In the overlay error model, the intrafield overlay errors include intrafield translation, isotropic magnification, reticle rotation, asymmetric magnification and asymmetric rotation, and the interfield overlay errors include interfield translation, scale error, wafer rotation and orthogonality error.

Claims

1. A method for analyzing overlay errors in lithography, comprising:

performing interfield sampling and intrafield sampling to sample a plurality of positions on a wafer;

measuring an overlay error value at each of the positions; and

using an overlay error model including coefficients of intrafield and interfield overlay errors of different types to fit the measured overlay error values with respect to the positions, wherein the intrafield overlay errors include intrafield translation, isotropic magnification, reticle rotation, asymmetric magnification and asymmetric rotation, and the interfield overlay errors include interfield translation, scale error, wafer rotation and orthogonality error, wherein a pattern of the interfield sampling comprises at least four fields having four different X-coordinates and four different Y-coordinates and the X-coordinates and the Y-coordinates are wafer coordinates relate to the center of the wafer, wherein each field is apart from a center of the wafer by at least 50% of a radius of the wafer, and an angle between any two fields with respect to the center of the wafer is at least 30°

.

2. The method of claim 1, wherein the coefficients are estimated using a least square method in the fitting.

3. The method of claim 1, wherein the overlay error model is expressed as the following simultaneous polynomial equations:

d_x+X=T_x+X+S_XX−

(θ

_w+φ

)Y+(M_i+M_a)x−

(θ

_r+θ

_a)y+ε

_x+X 

 

(1)

d_y+Y=T_y+Y+S_YY+θ

_wX+(M_i−

M_a)y+(θ

_r−

θ

_a)x+ε

_y+Y 

 

(2)

wherein

x and y are intrafield coordinates;

X and Y are interfield coordinates;

d_x+X is the sum of the intrafield and interfield overlay errors in x-axis direction;

d_y+Y is the sum of the intrafield and interfield overlay errors in y-axis direction;

T_x+X is the sum of the intrafield and interfield translation overlay errors in x-axis direction;

T_y+Y is the sum of the intrafield and interfield translation overlay errors my-axis direction;

S_X is a scale in x-axis direction;

S_Y is a scale in y-axis direction;

θ

_w is a coefficient of wafer rotation;

φ

is an orthogonality error;

M_i is a coefficient of isotropic magnification;

M_a is a coefficient of asymmetric magnification;

θ

_r is a coefficient of reticle rotation;

θ

_a is a coefficient of asymmetric rotation; and

ε

_x+X and ε

_y+Y are residue overlay errors in x-axis direction and in y-axis direction, respectively.

4. The method of claim 1, wherein the pattern of the interfield sampling further comprises a field around the center of the wafer.

5. The method of claim 4, wherein the distance between the center of the wafer and the field around the center is no more than 1/15 of the radius of the wafer.

6. The method of claim 1, wherein a pattern of the intrafield sampling comprises at least five positions with four around four corners of a field and one around the center of the field.

7. The method of claim 1, wherein

a pattern of the intrafield sampling comprises at least four positions around four corners of a field.

8. The method of claim 7, wherein the pattern of the intrafield sampling further comprises a position around the center of the field.

9. The method of claim 7, wherein the pattern of the interfield sampling further comprises a field around the center of the wafer.

10. The method of claim 9, wherein the distance between the center of the wafer and the field round the center is no more than 1/15 of the radius of the wafer.

11. The method of claim 7, wherein the pattern of the intrafield sampling further comprises a position around the center of the field, and the pattern of the interfield sampling further comprises a field around the center of the wafer.