Scalable subsystem architecture having integrated cooling channels

• US 7,586,747 B2
• Filed: 07/27/2006
• Issued: 09/08/2009
• Est. Priority Date: 08/01/2005
• Status: Expired due to Fees

• Current Assignee: Salmon Technologies LLC
• Original Assignee: Salmon Technologies LLC
• Inventors: Salmon, Peter C.
• Primary Examiner(s): CHERVINSKY, BORIS LEO
• Application Number:
  US11/495,954
• Publication Number:
  US 20070025079A1
• Time in Patent Office: 1,139 Days
• Field of Search: None
• US Class Current: 361/699
• CPC Class Codes: G02B 6/43 Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/467 by flowing gases, e.g. air H01L23/473 takes precedence
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base

Abstract

A method for building scalable electronic subsystems is described. Stackable modules employ copper substrates with solder connections between modules, and a ball grid array interface is provided at the bottom of the stack. A cooling channel is optionally provided between each pair of modules. Each module is re-workable because all integrated circuit attachments within the module employ re-workable flip chip connectors. Also, defective modules can be removed from the stack by directing hot inert gas at externally accessible solder connections.

Claims

1. An electronic subsystem comprising:

a first stackable module including;

a first substrate having first and second surfaces and a first conductive feedthrough extending between the first and second surfaces;

an integrated circuit mounted on the first substrate;

a second substrate having first and second surfaces and a second conductive feedthrough extending between the first and second surfaces of the second substrate, the second conductive feedthrough electrically coupled to the first conductive feedthrough;

a cooling channel beneath the first substrate, the cooling channel defined by the first and second substrates;

an interconnector electrically coupled to the first and second conductive feedthroughs, the interconnector forming the electronic subsystem by permitting the first stackable module to couple to an additional stackable module; and

a ball grid array interface coupled to the interconnector for communication with the first and second stackable modules.

2. The electronic subsystem of claim 1 wherein the interconnector includes a solder connection, and the electronic subsystem includes a second stackable module connected to the interconnector.

3. The electronic subsystem of claim 1 wherein the stackable module includes a connection to an optical fiber for high bandwidth communications.

4. The electronic subsystem of claim 1 wherein said stackable module includes a copper substrate.

5. The electronic subsystem of claim 1 wherein said module includes direct chip attachments between the integrated circuit and the first substrate employing flip chip connectors.

6. An electronic subsystem comprising:

a first stackable module including;

a first substrate having first and second surfaces and a first conductive feedthrough extending between the first and second surfaces;

an integrated circuit mounted on the first substrate;

a second substrate having first and second surfaces and a second conductive feedthrough extending between the first and second surfaces of the second substrate, the second conductive feedthrough electrically coupled to the first conductive feedthrough;

a cooling channel beneath the first substrate, the cooling channel defined by the first and second substrates; and

,

an interconnector including a pillar for pillar in well connectors, the interconnector electrically coupled to the first and second conductive feedthroughs, the interconnector forming the electronic subsystem by permitting the first stackable module to couple to an additional stackable module.

7. An electronic subsystem comprising:

a first stackable module including;

a first copper substrate having first and second surfaces and a first glass-sealed copper feedthrough extending between the first and second surfaces;

an integrated circuit mounted on the first substrate;

a second copper substrate having first and second surfaces and a second glass-sealed copper feedthrough extending between the first and second surfaces of the second substrate, the second glass-sealed copper feedthrough electrically coupled to the first glass-sealed copper feedthrough;

a cooling channel beneath the first substrate, the cooling channel defined by the first and second substrates; and

,

an interconnector electrically coupled to the first and second glass-sealed copper feedthroughs, the interconnector forming the electronic subsystem by permitting the first stackable module to couple to an additional stackable module.

8. The electronic subsystem of claim 7 wherein interconnection circuits are fabricated on said copper substrate.

9. A re-workable and well-cooled electronic subsystem comprising:

integrated circuit chips attached to stackable modules using re-workable flip chip connectors, each of which include a conductive bump or pillar inserted into a well filled with conductive material;

spacers providing electrical feed throughs and a sealed cooling channel between each of said stackable modules;

coolant flowing in said cooling channels; and

,

solder connections between said modules and said spacers in said stack that are accessible to directed jets of hot inert gas for melting said solder in selected ones of said connections for performing said rework of said subsystem.

10. The electronic subsystem of claim 9 wherein said conductive material is a conductive powder.

11. The electronic subsystem of claim 10 wherein said conductive powder includes particles of alloy 80Au20Sn.

12. The electronic subsystem of claim 9 wherein said conductive material includes a solder.

13. The electronic subsystem of claim 9 wherein said bumps or pillars have a height to width ratio of 2.5-10, providing a mechanically compliant interface.

14. The re-workable subsystem of claim 9 wherein said integrated circuit chips include a plurality of circuit types selected from digital, analog, RF, optical, electro-optical, and integrated passives.

15. The re-workable subsystem of claim 9 wherein said stackable modules are hermetic.