Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
First Claim
1. A method for operating a memory device comprising a first memory member and a second memory member arranged in electrical series, the first and second memory members each programmable to a plurality of resistance states, the method comprising:
- applying a first voltage scheme across the series arrangement of the first and second memory members to change the memory device from a first logic state to a second logic state, the first and second logic states corresponding to the same resistance state of the first memory member and corresponding to different resistance states of the second memory member; and
applying a second voltage scheme across the series arrangement of the first and second memory members to change the memory device from the first logic state to a third logic state, the first and third logic states corresponding to different resistance states of the first memory member and corresponding to the same resistance states of the second memory member.
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Abstract
A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f) R. The logic “1” state is represented by a mathematical expression (n+f) R. The logic “2” state is represented by a mathematical expression (1+nf) R. The logic “3” state is represented by a mathematical expression n(1+f) R.
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Citations
16 Claims
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1. A method for operating a memory device comprising a first memory member and a second memory member arranged in electrical series, the first and second memory members each programmable to a plurality of resistance states, the method comprising:
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applying a first voltage scheme across the series arrangement of the first and second memory members to change the memory device from a first logic state to a second logic state, the first and second logic states corresponding to the same resistance state of the first memory member and corresponding to different resistance states of the second memory member; and applying a second voltage scheme across the series arrangement of the first and second memory members to change the memory device from the first logic state to a third logic state, the first and third logic states corresponding to different resistance states of the first memory member and corresponding to the same resistance states of the second memory member. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification