Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states

• US 7,586,778 B2
• Filed: 06/05/2008
• Issued: 09/08/2009
• Est. Priority Date: 10/24/2006
• Status: Expired due to Fees

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Ho, ChiaHua, Hsieh, Kuang Yeu
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US12/134,117
• Publication Number:
  US 20080285330A1
• Time in Patent Office: 460 Days
• Field of Search: 365/100, 365/113
• US Class Current: 365/148
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/5664 using organic memory material storage elements
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/0016 comprising polymers
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f) R. The logic “1” state is represented by a mathematical expression (n+f) R. The logic “2” state is represented by a mathematical expression (1+nf) R. The logic “3” state is represented by a mathematical expression n(1+f) R.

Claims

1. A method for operating a memory device comprising a first memory member and a second memory member arranged in electrical series, the first and second memory members each programmable to a plurality of resistance states, the method comprising:

applying a first voltage scheme across the series arrangement of the first and second memory members to change the memory device from a first logic state to a second logic state, the first and second logic states corresponding to the same resistance state of the first memory member and corresponding to different resistance states of the second memory member; and

applying a second voltage scheme across the series arrangement of the first and second memory members to change the memory device from the first logic state to a third logic state, the first and third logic states corresponding to different resistance states of the first memory member and corresponding to the same resistance states of the second memory member.

2. The method of claim 1, further comprising applying a third voltage scheme across the series arrangement of the first and second memory members to change the memory device from the first logic state to a fourth logic state, the first and fourth logic states corresponding to different resistance states of the first memory member and corresponding to different resistance states of the second memory member.

3. The method of claim 1, wherein the applying a first voltage scheme comprises applying a first voltage across the series arrangement of the first and second memory members to maintain the resistance state of the first memory member and change the resistance state of the second memory member.

4. The method of claim 3, wherein the applying a second voltage scheme comprises applying a second voltage across the series arrangement of the first and second memory members to change the resistance state of the first memory member and maintain the resistance state of the second memory member.

5. The method of claim 4, further comprising applying a third voltage scheme across the series arrangement of the first and second memory members to change the memory device from the first logic state to a fourth logic state, the first and fourth logic states corresponding to different resistance states of the first memory member and corresponding to different resistance states of the second memory member.

6. The method of claim 5, wherein applying a third voltage scheme comprises:

applying a third voltage across the series arrangement of the first and second memory members to change the memory device from the first logic state to a transition state, the third voltage adapted to maintain the resistance state of the first memory member and change the resistance state of the second memory member; and

applying a fourth voltage across the series arrangement of the first and second memory members to change the memory device from the transition state to the second logic state, the fourth voltage adapted to change the resistance state of the first memory member and maintain the resistance state of the second memory member.

7. The method of claim 6, wherein the second logic state and the transition state correspond to the same resistance state of the first memory member and the same resistance state of the second memory member.

8. The method of claim 7, wherein:

the first and second memory members are each programmable to respective low and high resistance states;

the first logic state corresponds to the low resistance state of the first memory member and the high resistance state of the second memory member;

the second logic state corresponds to the low resistance state of the first memory member and the low resistance state of the second memory member;

the third logic state corresponds to the high resistance state of the first memory member and the high resistance state of the second memory member; and

the fourth logic state corresponds to the high resistance state of the first memory member and the low resistance state of the second memory member.

9. The method of claim 7, wherein:

the first and second memory members are each programmable to respective low and high resistance states;

the first logic state corresponds to the high resistance state of the first memory member and the low resistance state of the second memory member;

the second logic state corresponds to the high resistance state of the first memory member and the high resistance state of the second memory member;

the third logic state corresponds to the low resistance state of the first memory member and the low resistance state of the second memory member; and

the fourth logic state corresponds to the low resistance state of the first memory member and the high resistance state of the second memory member.

10. The method of claim 1, wherein the applying a first voltage scheme comprises:

applying a first voltage across the series arrangement of the first and second memory members to change the memory device from the first logic state to a transition state, the first voltage adapted to change the resistance states of both the first and second memory members; and

applying a second voltage across the series arrangement of the first and second memory members to change the memory device from the transition state to the second logic state, the second voltage adapted change the resistance state of the first memory member and maintain the resistance state of the second memory member.

11. The method of claim 10, wherein the applying a second voltage scheme comprises applying a third voltage across the series arrangement of the first and second memory members to change the resistance state of the first memory member and maintain the resistance state of the second memory member.

12. The method of claim 11, further comprising applying a third voltage scheme across the series arrangement of the first and second memory members to change the memory device from the first logic state to a fourth logic state, the first and fourth logic states corresponding to different resistance states of the first memory member and corresponding to different resistance states of the second memory member.

13. The method of claim 12, wherein the applying a third voltage scheme comprises applying a fourth voltage across the series arrangement of the first and second memory members to change the resistance states of both the first and second memory members.

14. The method of claim 13, wherein the fourth logic state and the transition state correspond to the same resistance state of the first memory member and the same resistance state of the second memory member.

15. The method of claim 14, wherein:

the first and second memory members are each programmable to respective low and high resistance states;

the first logic state corresponds to the low resistance state of the first memory member and the low resistance state of the second memory member;

the second logic state corresponds to the low resistance state of the first memory member and the high resistance state of the second memory member;

the third logic state corresponds to the high resistance state of the first memory member and the low resistance state of the second memory member; and

the fourth logic state corresponds to the high resistance state of the first memory member and the high resistance state of the second memory member.

16. The method of claim 14, wherein:

the first and second memory members are each programmable to respective low and high resistance states;

the first logic state corresponds to the high resistance state of the first memory member and the high resistance state of the second memory member;

the second logic state corresponds to the high resistance state of the first memory member and the low resistance state of the second memory member;

the third logic state corresponds to the low resistance state of the first memory member and the high resistance state of the second memory member; and

the fourth logic state corresponds to the low resistance state of the first memory member and the low resistance state of the second memory member.