Using receive diversity to extend standby time in QPCH mode

• US 7,586,863 B2
• Filed: 04/08/2005
• Issued: 09/08/2009
• Est. Priority Date: 04/08/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kurapati, Nagabhushana Rao, Tu, Kuang-Hsuan
• Primary Examiner(s): Urban; Edward
• Assistant Examiner(s): Hannon; Christian A
• Application Number:
  US11/102,065
• Publication Number:
  US 20060227734A1
• Time in Patent Office: 1,614 Days
• Field of Search: 370/311, 370/342, 370/441, 455/133, 455/135, 455/140, 455/273, 455/277.1, 455/277.2
• US Class Current: 370/311
• CPC Class Codes: H04B 7/0882 using post-detection diversity
• CPC Class Codes: H04W 52/0245 according to signal strength
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The standby time of a CDMA cell phone is extended by using two receive chains to monitor the Quick Paging Channel (QPCH) when the signal-to-noise ratio falls within a predetermined range. Monitoring the QPCH saves battery power by obviating the need to monitor the general paging message unless quick paging (PI) bits are set. The QPCH is not monitored, however, in noisy environments where PI bits are incorrectly detected causing the paging message to be needlessly monitored. Power is saved by monitoring the QPCH in noisier environments without increasing the incorrect detection rate. Incorrect detection is reduced in the predetermined range by using an additional receive chain to achieve receive diversity. Although additional power is consumed by the second receive chain in the predetermined range, the power saved by not demodulating the paging message at each slot more than compensates for the additional power consumed by the second receive chain.

Claims

1. A method comprising:

(a) demodulating a first quick paging bit from a quick paging channel received both through a first receive chain and through a second receive chain;

(b) determining a signal-to-noise ratio of the first paging bit;

when the signal-to-noise ratio is above a predetermined range, performing the steps of;

(c) turning off the second receive chain; and

(d) demodulating a second quick paging bit from the quick paging channel received through the first receive chain.

2. The method of claim 1, wherein the demodulating the first quick paging bit involves despreading with a pseudonoise sequence and applying an inverse Walsh code.

3. The method of claim 1, wherein the first quick paging bit is demodulated from I and Q samples, and wherein the demodulating the first quick paging bit in (a) is performed after the I and Q samples have been stored in and read from random access memory.

4. The method of claim 1, wherein the signal-to-noise ratio is the signal-to-noise ratio of a pilot channel.

5. The method of claim 1, if the signal-to-noise ratio is below the predetermined range, further comprising the steps of:

(e) turning off the second receive chain; and

(f) demodulating a general paging message from a regular paging channel received through the first receive chain.

6. The method of claim 1, if the signal-to-noise ratio falls within the predetermined range, further comprising:

(e) demodulating a third quick paging bit from the quick paging channel received both through the first receive chain and through the second receive chain.

31. The method of claim 1, further comprising:

(e) determining a power setting of the quick paging channel, wherein the first quick paging bit is demodulated in (d) depending on the power setting of the quick paging channel.

7. A method comprising:

(a) demodulating first I and Q samples received from a first receive chain to obtain a value of a first quick paging bit of a quick paging channel;

(b) determining that a signal-to-noise ratio of the first I and Q samples falls within a predetermined range;

(c) turning on a second receive chain; and

(d) demodulating second I and Q samples received both from the first receive chain and from the second receive chain to obtain a second quick paging bit of the quick paging channel, wherein receiving from both the first receive chain and the second receive chain reduces a probability of incorrectly detecting the second PI bit.

8. The method of claim 7, wherein the demodulating the first I and Q samples involves despreading with a pseudonoise sequence and applying an inverse Walsh code.

9. The method of claim 7, wherein the demodulating the first I and Q samples is performed after the first I and Q samples have been stored in and read from random access memory.

10. The method of claim 7, wherein the demodulating the first I and Q samples is performed in real time as the first I and Q samples are received from the first receive chain.

11. The method of claim 7, wherein the signal-to-noise ratio is the signal-to-noise ratio of a pilot channel obtained by demodulating the first I and Q samples.

12. The method of claim 7, further comprising:

(f) determining that a signal-to-noise ratio of the second I and Q samples falls below the predetermined range;

(g) turning off the second receive chain; and

(h) demodulating third I and Q samples received from the first receive chain to obtain a regular paging channel.

13. A circuit comprising:

means for demodulating first I and Q samples received from a first receive chain to obtain a value of a first quick paging bit of a quick paging channel;

means for determining that a signal-to-noise ratio of the first I and Q samples falls within a predetermined range;

means for turning on a second receive chain; and

means for demodulating second I and Q samples received both from the first receive chain and from the second receive chain to obtain a second quick paging bit of the quick paging channel wherein receiving from both the first receive chain and the second receive chain reduces a probability of incorrectly detecting the second PI bit.

14. The circuit of claim 13, further comprising:

means for determining that a signal-to-noise ratio of the second I and Q samples falls below the predetermined range;

means for turning off the second receive chain; and

means for demodulating third I and Q samples received from the first receive chain to obtain a regular paging channel.

15. A method comprising:

(a) demodulating first I and Q samples received from a first receive chain to obtain a value of a first quick paging bit of a quick paging channel;

(b) determining that the value of the first quick paging bit obtained by demodulating the first I and Q samples is incorrect;

(c) turning on a second receive chain; and

(d) demodulating second I and Q samples received both from the first receive chain and from the second receive chain to obtain a value of a second quick paging bit of the quick paging channel wherein receiving from both the first receive chain and the second receive chain reduces a probability of incorrectly detecting the second PI bit.

16. The method of claim 15, farther comprising between (a) and (b):

(a1) demodulating third I and Q samples received from the first receive chain to obtain a frame of a regular paging channel.

17. The method of claim 15, further comprising:

(e) determining that the value of the second quick paging bit obtained by demodulating the second I and Q samples is incorrect;

(f) turning off the second receive chain; and

(g) demodulating third I and Q samples received from the first receive chain to obtain a regular paging channel.

18. A processor readable medium encoded with processor executable instructions, operable in a wireless device to:

(a) demodulate first I and Q samples received from a first receive chain to obtain a value of a first quick paging bit of a quick paging channel;

(b) determine that the value of the first quick paging bit obtained by demodulating the first I and Q samples is incorrect;

(c) turn on a second receive chain; and

(d) demodulate second I and Q samples received both from the first receive chain and from the second receive chain to obtain a value of a second quick paging bit of the quick paging channel wherein receiving from both the first receive chain and the second receive chain reduces a probability of incorrectly detecting the second PI bit.

19. The processor-readable media of claim 18, and further for storing instructions operable in the wireless device between (a) and (b) to:

(a1) demodulate third I and Q samples received from the first receive chain to obtain a frame of a regular paging channel.

20. The computer-readable medium of claim 18, and further for storing instructions operable in the wireless device to:

(e) determine that the value of the second quick paging bit obtained by demodulating the second I and Q samples is incorrect;

(f) turn off the second receive chain; and

(g) demodulate third I and Q samples received from the first receive chain to obtain a regular paging channel.

21. A circuit comprising:

a microprocessor that determines a value of a quick paging bit demodulated from I and Q samples received from a first receive chain,;

a noise detector that determines a signal-to-noise ratio from the I and Q samples; and

a state machine that generates a receive chain control signal, wherein the receive chain control signal causes a second receive chain to be powered when the signal-to-noise ratio is within a predetermined range, wherein the second receive chain reduces a probability of incorrectly detecting a quick paging bit false alarm.

22. The circuit of claim 21, wherein the microprocessor determines a second value of a second quick paging bit demodulated from second I and Q samples received both from the first receive chain and from the second receive chain after the receive chain control signal causes the second receive chain to be powered.

23. The circuit of claim 21, wherein the receive chain control signal causes the second receive chain to be off when the signal-to-noise ratio is outside the predetermined range.

24. The circuit of claim 21, wherein the noise detector and the state machine are instructions operating on a processor, wherein the processor includes a processor-readable medium, and wherein the instructions are stored on the processor-readable medium.

25. The circuit of claim 21, wherein the noise detector is a portion of a processor.

26. The circuit of claim 21, further comprising:

a demodulation chain that receives the I and Q samples from the first receive chain and demodulates the quick paging bit from the I and Q samples in real time.

27. The circuit of claim 21, further comprising:

random access memory, wherein the I and Q samples are stored in the random access memory; and

an accumulator that receives the I and Q samples from the random access memory and demodulates the quick paging bit from the I and Q samples.

28. The circuit of claim 21, wherein the quick paging bit is demodulated from the I and Q samples by despreading the I and Q samples with a pseudonoise sequence and applying an inverse Walsh code.

29. A circuit comprising:

a microprocessor that determines a value of a quick paging bit, wherein the quick paging bit is demodulated from I and Q samples received from a first receive chain, wherein the I and Q samples exhibit a signal-to-noise ratio,; and

means for generating a receive chain control signal that causes a second receive chain to be powered when both the signal-to-noise ratio is within a predetermined range, wherein the second receive chain reduces a probability of incorrectly detecting a quick paging bit false alarm.

30. The circuit of claim 29, wherein the microprocessor determines a value of a second quick paging bit, wherein the second quick paging bit is demodulated from second I and Q samples received both from the first receive chain and from the second receive chain when the receive chain control signal causes the second receive chain to be powered.