Serializer-deserializer circuits formed from input-output circuit registers

• US 7,587,537 B1
• Filed: 11/30/2007
• Issued: 09/08/2009
• Est. Priority Date: 11/30/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Burney, Ali
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US11/998,603
• Time in Patent Office: 648 Days
• Field of Search: 326/86, 326/41, 710/106, 710/71
• US Class Current: 710/71
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H04L 63/1408 by monitoring network traffic monitoring network traffic per se H04L43/00
• CPC Class Codes: H04L 63/1425 Traffic logging, e.g. anomaly detection
• CPC Class Codes: H04L 63/1433 Vulnerability analysis
• CPC Class Codes: H04L 63/145 the attack involving the propagation of malware through the network, e.g. viruses, trojans or worms

Abstract

Input-output circuitry for integrated circuits such as programmable logic device integrated circuits is provided. The input-output circuitry can be configured to operate in a single-ended data mode or a serializer-deserializer mode using programmable routing circuitry such as programmable multiplexers. In single-ended data mode, data registers in the single-ended input-output circuitry may be used to handle transmitted and received single-ended data. In serializer-deserializer mode, the data registers may be configured to form a shift register. The shift register may be used in a serializer-deserializer circuit. Parallel-to-serial and serial-to-parallel data conversion operations may be performed using the shift register. The serializer-deserializer circuit may be connected to differential input-output circuitry such as a differential transmitter circuit or a differential receiver circuit. The data registers may be configured to operate as positive-edge-triggered or negative-edge-triggered devices.

Claims

1. Input-output circuitry that serves as an interface between core logic and input-output pins on an integrated circuit, comprising:

a plurality of data registers;

programmable circuitry that is configured to connect the data registers to form a serializer-deserializer shift register;

single-ended data input-output circuitry containing the plurality of data registers; and

differential signaling input-output circuitry.

2. The input-output circuitry defined in claim 1 wherein the programmable circuitry comprises programmable multiplexer circuitry.

5. The input-output circuitry defined in claim 1 wherein the differential signaling input-output circuitry comprises:

differential transmitter circuitry, wherein the serializer-deserializer shift register converts parallel data to serial data that is transmitted through a pair of the input-output pins by the differential transmitter circuitry.

6. The input-output circuitry defined in claim 1 wherein the differential signaling input-output circuitry comprises:

differential receiver circuitry that receives differential input data from a pair of the input-output pins and that produces corresponding single-ended serial data, wherein the serializer-deserializer shift register converts the serial data to parallel data.

7. The input-output circuitry defined in claim 1 wherein the differential signaling input-output circuitry comprises:

differential transmitter circuitry, wherein the serializer-deserializer shift register converts parallel data to serial data that is transmitted through a pair of the input-output pins by the differential transmitter circuitry; and

differential receiver circuitry that receives differential input data from the pair of input-output pins and that produces corresponding single-ended serial data, wherein the serializer-deserializer shift register converts the serial data to parallel data.

8. The input-output circuitry defined in claim 1 wherein the programmable circuitry comprises programmable multiplexer circuitry, wherein the single-ended data input-output circuitry comprises an output buffer and an output enable control circuit that controls the output buffer, and wherein the differential signaling input-output circuitry comprises:

differential transmitter circuitry, wherein the serializer-deserializer shift register converts parallel data to serial data that is transmitted through a pair of the input-output pins by the differential transmitter circuitry; and

differential receiver circuitry that receives differential input data from the pair of input-output pins and that produces corresponding single-ended serial data, wherein the serializer-deserializer shift register converts the serial data to parallel data.

3. Input-output circuitry that serves as an interface between core logic and input-output pins on an integrated circuit, comprising:

a plurality of data registers;

programmable circuitry that is configured to connect the data registers to form a serializer-deserializer shift register, wherein the plurality of data registers comprise programmable data registers that are selectively configured as positive-edge-triggered registers or negative-edge-triggered registers.

4. The input-output circuitry defined in claim 3 wherein the programmable circuitry comprises programmable multiplexer circuitry.

9. A method for selectively configuring input-output circuit data registers to form a serializer-deserializer shift register, comprising:

obtaining a logic design from a logic designer;

creating configuration data corresponding to the logic design; and

loading the configuration data into an integrated circuit to implement the logic design, wherein when the configuration data is loaded into the integrated circuit, the input-output circuit data registers are connected to form the serializer-deserializer shift register, wherein the input-output circuit data registers are contained within a programmable integrated circuit that has programmable elements and wherein loading the configuration data comprises loading the configuration data into the programmable elements.

10. The method defined in claim 9 wherein the input-output circuit data registers are contained within a single-ended data input-output circuit and wherein loading the configuration data comprises loading configuration data into programmable elements to configure the data registers in the single-ended data input-output circuit to form the serializer-deserializer shift register.

11. An integrated circuit comprising:

input-output pins;

core logic;

input-output circuitry connected between the input-output pins and the core logic;

a plurality of data registers in the input-output circuitry; and

programmable circuitry in the input-output circuitry that is selectively configured to connect the data registers to form a serializer-deserializer shift register, wherein the plurality of data registers comprise programmable data registers that are selectively configured as positive-edge-triggered registers or negative-edge-triggered registers.

12. The integrated circuit defined in claim 11 wherein the programmable circuitry comprises programmable multiplexer circuitry.

13. An integrated circuit comprising:

input-output pins;

core logic;

input-output circuitry connected between the input-output pins and the core logic;

a plurality of data registers in the input-output circuitry;

programmable circuitry in the input-output circuitry that is selectively configured to connect the data registers to form a serializer-deserializer shift register;

single-ended data input-output circuitry containing the plurality of data registers; and

differential transmitter circuitry, wherein the serializer-deserializer shift register converts parallel data to serial data that is transmitted through a pair of the input-output pins by the differential transmitter circuitry.

15. The integrated circuit defined in claim 13 further comprising:

differential receiver circuitry that receives differential input data from the pair of input-output pins and that produces corresponding single-ended serial data, wherein the serializer-deserializer shift register converts the serial data to parallel data.

14. An integrated circuit comprising:

input-output pins;

core logic;

input-output circuitry connected between the input-output pins and the core logic;

a plurality of data registers in the input-output circuitry;

programmable circuitry in the input-output circuitry that is selectively configured to connect the data registers to form a serializer-deserializer shift register;

single-ended data input-output circuitry containing the plurality of data registers; and

differential receiver circuitry that receives differential input data from a pair of the input-output pins and that produces corresponding single-ended serial data, wherein the serializer-deserializer shift register converts the serial data to parallel data.